2007 |
28 | EE | Chun-Lin Yang,
Yuang-Cheng Hsiao,
Shyue-Kung Lu:
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults.
PRDC 2007: 224-231 |
2006 |
27 | EE | Shyue-Kung Lu,
Ting-Yu Chen,
Wei-Yuan Liu:
Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits.
PRDC 2006: 97-104 |
26 | EE | Ming-Wei Wu,
Yennun Huang,
Ing-Yi Chen,
Shyue-Kung Lu,
Sy-Yen Kuo:
A Scalable Port Forwarding for P2P-Based Wi-Fi Applications.
WASA 2006: 26-37 |
25 | EE | Shyue-Kung Lu,
Yu-Chen Tsai,
Chih-Hsien Hsu,
Kuo-Hua Wang,
Cheng-Wen Wu:
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy.
IEEE Trans. VLSI Syst. 14(1): 34-42 (2006) |
24 | EE | Shyue-Kung Lu,
Chih-Hsien Hsu:
Fault tolerance techniques for high capacity RAM.
IEEE Transactions on Reliability 55(2): 293-306 (2006) |
2005 |
23 | EE | Ming-Wei Wu,
Yennun Huang,
Shyue-Kung Lu,
Ing-Yi Chen,
Sy-Yen Kuo:
A Multi-Faceted Approach towards Spam-Resistible Mail.
PRDC 2005: 208-218 |
22 | EE | Shyue-Kung Lu,
Jen-Sheng Shih,
Shih-Chang Huang:
Design-for-testability and fault-tolerant techniques for FFT processors.
IEEE Trans. VLSI Syst. 13(6): 732-741 (2005) |
2004 |
21 | EE | Shyue-Kung Lu,
Hung-Chin Wu,
Shoei-Jia Yan,
Yu-Cheng Tsai:
Testing and Diagnosis Techniques for LUT-Based FPGA's.
Asian Test Symposium 2004: 414-419 |
20 | EE | Shyue-Kung Lu,
Mau-Jung Lu:
Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model.
DELTA 2004: 416-418 |
19 | EE | Shyue-Kung Lu,
Shih-Chang Huang:
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs.
MTDT 2004: 60-64 |
18 | EE | Shyue-Kung Lu,
Chien-Hung Yeh,
Han-Wen Lin:
Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors.
PRDC 2004: 321-326 |
2003 |
17 | EE | Shyue-Kung Lu,
Jian-Long Chen,
Cheng-Wen Wu,
Ken-Feng Chang,
Shi-Yu Huang:
Combinational circuit fault diagnosis using logic emulation.
ISCAS (5) 2003: 549-552 |
16 | EE | Shyue-Kung Lu:
A Novel Built-In Self-Repair Approach for Embedded RAMs.
J. Electronic Testing 19(3): 315-324 (2003) |
15 | EE | Hong-Chou Kao,
Ming-Fu Tsai,
Shi-Yu Huang,
Cheng-Wen Wu,
Wen-Feng Chang,
Shyue-Kung Lu:
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.
J. Inf. Sci. Eng. 19(4): 571-587 (2003) |
2002 |
14 | EE | Chih-Hsien Hsu,
Shyue-Kung Lu:
Fault-tolerance design of memory systems based on DBL structures.
APCCAS (1) 2002: 221-224 |
13 | EE | Shyue-Kung Lu,
Chien-Hung Yeh:
Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks.
Asian Test Symposium 2002: 230- |
12 | EE | Shyue-Kung Lu,
Chung-Yang Chen:
Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's.
Asian Test Symposium 2002: 236-241 |
11 | EE | Shyue-Kung Lu,
Chien-Hung Yeh:
Enhancing Delay Fault Testability for Iterative Logic Array.
PRDC 2002: 283-292 |
2001 |
10 | EE | Shyue-Kung Lu,
Chih-Hsien Hsu:
Built-In self-repair for divided word line memory.
ISCAS (4) 2001: 13-16 |
9 | EE | Chih-Hsien Hsu,
Shyue-Kung Lu,
Sy-Yen Kuo:
Novel Fault-Tolerant Techniques for High Capacity RAMs.
PRDC 2001: 11-18 |
2000 |
8 | EE | Shyue-Kung Lu,
Jeh-Sheng Shih,
Cheng-Wen Wu:
A Testable/Fault Tolerant FFT Processor Design.
Asian Test Symposium 2000: 429- |
7 | EE | Shyue-Kung Lu,
Jen-Sheng Shih:
Testing Configurable LUT-Based FPGAs.
J. Inf. Sci. Eng. 16(5): 733-750 (2000) |
1999 |
6 | EE | Shyue-Kung Lu,
Tsung-Ying Lee,
Cheng-Wen Wu:
Defect Level Prediction Using Multi-Model Fault Coverage.
Asian Test Symposium 1999: 301- |
5 | EE | Shyue-Kung Lu,
Cheng-Wen Wu:
A novel approach to testing LUT-based FPGAs.
ISCAS (1) 1999: 173-177 |
1997 |
4 | | Shyue-Kung Lu,
Sy-Yen Kuo,
Cheng-Wen Wu:
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy.
IEEE Trans. Computers 46(9): 1028-1034 (1997) |
1996 |
3 | EE | Shyue-Kung Lu,
Cheng-Wen Wu,
Ruei-Zong Hwang:
Cell delay fault testing for iterative logic arrays.
J. Electronic Testing 9(3): 311-316 (1996) |
1995 |
2 | EE | Shyue-Kung Lu,
Jen-Chuan Wang,
Cheng-Wen Wu:
C-testable design techniques for iterative logic arrays.
IEEE Trans. VLSI Syst. 3(1): 146-152 (1995) |
1991 |
1 | | Cheng-Wen Wu,
Shyue-Kung Lu:
Designing Self-Testable Cellular Arrays.
ICCD 1991: 110-113 |