ISQED 2007:
San Jose,
California,
USA
8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA.
IEEE Computer Society 2007, ISBN 978-0-7695-2795-6 BibTeX
Tutorials
Evening Panel Discussion EP1
Plenary Session 1P
Session 1A:
Design for Manufacturing
- Duane S. Boning, Karthik Balakrishnan, Hong Cai, Nigel Drego, Ali Farahanchi, Karen Gettings, Daihyun Lim, Ajay Somani, Hayden Taylor, Daniel Truque, Xiaolin Xie:
Variation.
15-20
Electronic Edition (link) BibTeX
- Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu:
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.
21-26
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- Rajani Kuchipudi, Hamid Mahmoodi:
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.
27-32
Electronic Edition (link) BibTeX
- Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
33-40
Electronic Edition (link) BibTeX
Session 1B:
Device and Circuit Reliability
- Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao, Kishore Singhal, Dino Toffolon:
A New Simulation Method for NBTI Analysis in SPICE Environment.
41-46
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- Xiangning Yang, Kewal K. Saluja:
Combating NBTI Degradation via Gate Sizing.
47-52
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- Benoit Dubois, Jean-Baptiste Kammerer, Luc Hebrard, Francis Braun:
Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability.
53-58
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- Aram Shin, Sang Jun Hwang, Seung Woo Yu, Man Young Sung:
A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays.
59-66
Electronic Edition (link) BibTeX
Session 1C:
Power and Thermal Management
Session 1D:
Analog and Mixed Signal Design
- Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik:
Low Voltage Buffered Bandgap Reference.
93-97
Electronic Edition (link) BibTeX
- Pengfei Li, Rizwan Bashirullah:
A DLL Based Multiphase Hysteretic DC-DC Converter.
98-101
Electronic Edition (link) BibTeX
- Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen:
Statistical Timing Analysis Considering Spatial Correlations.
102-107
Electronic Edition (link) BibTeX
- Liang Rong, E. Martin I. Gustafsson, Ana Rusu, Mohammed Ismail:
Systematic Design of a Flash ADC for UWB Applications.
108-114
Electronic Edition (link) BibTeX
Luncheon Speech
Session 2A:
Quality and Reliability
- Arthur Nieuwoudt, Yehia Massoud:
Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions.
119-126
Electronic Edition (link) BibTeX
- Tamer Cakici, Kee-Jong Kim, Kaushik Roy:
FinFET Based SRAM Design for Low Standby Power Applications.
127-132
Electronic Edition (link) BibTeX
- Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton:
Compact Modeling of a PD SOI MESFET for Wide Temperature Designs.
133-138
Electronic Edition (link) BibTeX
- Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
Modeling of PMOS NBTI Effect Considering Temperature Variation.
139-144
Electronic Edition (link) BibTeX
- Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong:
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.
145-152
Electronic Edition (link) BibTeX
Session 2B:
Advances in Timing and Power in Physical Design
- Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry:
A Low-Power Multi-Pin Maze Routing Methodology.
153-158
Electronic Edition (link) BibTeX
- Pei-Yu Huang, Huan-Yu Chou, Yu-Min Lee:
An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis.
159-164
Electronic Edition (link) BibTeX
- Gustavo R. Wilke, Rajeev Murgai:
Design and Analysis of "Tree+Local Meshes" Clock Architecture.
165-170
Electronic Edition (link) BibTeX
- Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi:
An Efficient Algorithm for RLC Buffer Insertion.
171-175
Electronic Edition (link) BibTeX
- Nahmsuk Oh, Alireza Kasnavi, Peivand F. Tehrani:
Fast Crosstalk Repair by Quick Timing Change Estimation.
176-184
Electronic Edition (link) BibTeX
Session 2C:
Power-Aware System Design Methodologies
- Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson:
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
185-191
Electronic Edition (link) BibTeX
- Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj:
Cross Layer Error Exploitation for Aggressive Voltage Scaling.
192-197
Electronic Edition (link) BibTeX
- Hwisung Jung, Massoud Pedram:
A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems.
198-203
Electronic Edition (link) BibTeX
- Yongpan Liu, Huazhong Yang, Robert P. Dick, Hui Wang, Li Shang:
Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems.
204-209
Electronic Edition (link) BibTeX
- Foad Dabiri, Roozbeh Jafari, Ani Nahapetian, Majid Sarrafzadeh:
A Unified Optimal Voltage Selection Methodology for Low-Power Systems.
210-218
Electronic Edition (link) BibTeX
Session 2D:
Poster Papers
- Charbel J. Akl, Magdy A. Bayoumi:
Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion.
219-224
Electronic Edition (link) BibTeX
- Bi Yuan, Yi Zhang, Lili He:
A 8b 10Ms/s Low Power Pipelined A/D Converter.
225-228
Electronic Edition (link) BibTeX
- Yamei Li, Lili He:
First-Order Continuous-Time Sigma-Delta Modulator.
229-232
Electronic Edition (link) BibTeX
- Yokesh Kumar, Prosenjit Gupta:
Reducing EPL Alignment Errors for Large VLSI Layouts.
233-238
Electronic Edition (link) BibTeX
- Zhiyu Liu, Volkan Kursun:
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.
239-244
Electronic Edition (link) BibTeX
- Taeyong Je, Yungseon Eo:
Efficient Signal Integrity Verification of Multi-Coupled Transmission Lines with Asynchronously Switching Non-Linear Drivers.
245-250
Electronic Edition (link) BibTeX
- Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.
251-256
Electronic Edition (link) BibTeX
- Bao Liu:
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations.
257-262
Electronic Edition (link) BibTeX
- Xudong Niu, Yan Song, Bo Li, Wei Bian, Yadong Tao, Feng Liu, Jinhua Hu, Yu Chen, Frank He:
Tests on Symmetry and Continuity between BSIM4 and BSIM5.
263-268
Electronic Edition (link) BibTeX
- Naiyong Jin, Taoyong Ni:
Interface Specification Assurance Methods.
269-274
Electronic Edition (link) BibTeX
- Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan:
Multi-Dimensional Circuit and Micro-Architecture Level Optimization.
275-280
Electronic Edition (link) BibTeX
- Nigel Drego, Anantha Chandrakasan, Duane S. Boning:
A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays.
281-286
Electronic Edition (link) BibTeX
- Rishi Bhooshan:
Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits.
287-292
Electronic Edition (link) BibTeX
- Alfred L. Crouch, Phil Burlison, Dennis J. Ciplickas:
Processing High Volume Scan Test Results for Yield Learning.
293-298
Electronic Edition (link) BibTeX
- Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
299-304
Electronic Edition (link) BibTeX
- David Rennie, Manoj Sachdev:
Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits.
305-310
Electronic Edition (link) BibTeX
- Daniela De Venuto, Bruno Riccò:
Inductive Fault Analysis for Test and Diagnosis of DNA Sensor Arrays.
311-316
Electronic Edition (link) BibTeX
- Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy:
Fine-Grained Redundancy in Adders.
317-321
Electronic Edition (link) BibTeX
- Abby A. Ilumoka, Hong Lang Tan:
MEMS Failure Probability Prediction and Quality Enhancement Using Neural Networks.
322-326
Electronic Edition (link) BibTeX
- Venkataraman Mahalingam, N. Ranganathan:
Variation Aware Timing Based Placement Using Fuzzy Programming.
327-332
Electronic Edition (link) BibTeX
- Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Variation Analysis of CAM Cells.
333-338
Electronic Edition (link) BibTeX
- Qi Lin, Mei Ma, Tony Vo, Jenny Fan, Xin Wu, Richard Li, Xiao-Yu Li:
Design-for-Manufacture for Multi Gate Oxide CMOS Process.
339-343
Electronic Edition (link) BibTeX
- Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho:
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
344-349
Electronic Edition (link) BibTeX
- Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong:
Power Delivery Aware Floorplanning for Voltage Island Designs.
350-355
Electronic Edition (link) BibTeX
- Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy:
Passive Modeling of Interconnects by Waveform Shaping.
356-361
Electronic Edition (link) BibTeX
- Kaijian Shi, Zhian Lin, Yi-Min Jiang:
A Power Network Synthesis Method for Industrial Power Gating Designs.
362-367
Electronic Edition (link) BibTeX
- Yuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi:
Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint.
368-373
Electronic Edition (link) BibTeX
- Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato:
Challenges in Evaluations for a Typical-Case Design Methodology.
374-379
Electronic Edition (link) BibTeX
- Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew:
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.
380-385
Electronic Edition (link) BibTeX
- Xiaofang Wang, Sotirios G. Ziavras:
Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.
386-391
Electronic Edition (link) BibTeX
- Gautam Kumar Singh, Santosh Kumar Panigrahi:
A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-Heating.
392-397
Electronic Edition (link) BibTeX
- Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan:
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.
398-403
Electronic Edition (link) BibTeX
- Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
Built-In Test of RF Mixers Using RF Amplitude Detectors.
404-409
Electronic Edition (link) BibTeX
- Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas:
Glitch Control with Dynamic Receiver Threshold Adjustment.
410-415
Electronic Edition (link) BibTeX
- Yong Sin Kim, Sung-Mo Kang:
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O.
416-419
Electronic Edition (link) BibTeX
- Manoj Kumar Goparaju, Spyros Tragoudas:
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations.
420-425
Electronic Edition (link) BibTeX
- Kumar Yelamarthi, Chien-In Henry Chen:
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.
426-431
Electronic Edition (link) BibTeX
- Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud:
Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization.
432-437
Electronic Edition (link) BibTeX
- Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh:
System Level Estimation of Interconnect Length in the Presence of IP Blocks.
438-443
Electronic Edition (link) BibTeX
- Rasit Onur Topaloglu:
Energy-Minimization Model for Fill Synthesis.
444-451
Electronic Edition (link) BibTeX
- Santosh Shah, Arani Sinha, Li Song, Narain D. Arora:
On-Chip Inductance in X Architecture Enabled Design.
452-457
Electronic Edition (link) BibTeX
- Ashok Narasimhan, Ramalingam Sridhar:
Impact of Variability on Clock Skew in H-tree Clock Networks.
458-466
Electronic Edition (link) BibTeX
Session 3A:
Electrical Quality
- Andrew B. Kahng, Rasit Onur Topaloglu:
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances.
467-474
Electronic Edition (link) BibTeX
- Jeong-Yeol Kim, Ho-Soon Shin, Jong-Bae Lee, Moon-Hyun Yoo, Jeong-Taek Kong:
SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design.
475-480
Electronic Edition (link) BibTeX
- Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann:
Pareto-Front Computation and Automatic Sizing of CPPLLs.
481-486
Electronic Edition (link) BibTeX
- Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco:
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization.
487-494
Electronic Edition (link) BibTeX
Session 3B:
Analog and RF Testing
Session 3C:
Low Power Circuits
Plenary Session 2P
Session 4A:
Package Circuit Co-Design
- Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu:
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method.
567-572
Electronic Edition (link) BibTeX
- Eunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang:
Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design.
573-579
Electronic Edition (link) BibTeX
- Syed M. Alam, Robert E. Jones, Shahid Rauf, Ritwik Chatterjee:
Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology.
580-585
Electronic Edition (link) BibTeX
- Juan Pablo Martinez Brito, Hamilton Klimach, Sergio Bampi:
A Design Methodology for Matching Improvement in Bandgap References.
586-594
Electronic Edition (link) BibTeX
Session 4B:
High Level Optimization
Session 4C:
Interconnects and Power Grids
- Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw:
Self-Time Regenerators for High-Speed and Low-Power Interconnect.
621-626
Electronic Edition (link) BibTeX
- Hong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh:
Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization.
627-632
Electronic Edition (link) BibTeX
- Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu:
General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.
633-638
Electronic Edition (link) BibTeX
- Mini Nanua, David Blaauw:
Investigating Crosstalk in Sub-Threshold Circuits.
639-646
Electronic Edition (link) BibTeX
Session 4D:
Parametric Variations in Design
Luncheon Panel Discussion LP2
Session 5A:
DFM Statistics
- Ayhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh:
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization.
677-684
Electronic Edition (link) BibTeX
- Amith Singhee, Rob A. Rutenbar:
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis.
685-692
Electronic Edition (link) BibTeX
- Robert C. Aitken:
Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below.
693-698
Electronic Edition (link) BibTeX
- Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski:
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology.
699-702
Electronic Edition (link) BibTeX
- Uthman Alsaiari, Resve Saleh:
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy.
703-710
Electronic Edition (link) BibTeX
Session 5B:
Timing Test and Reliability
- Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham:
Small-Delay Defect Detection in the Presence of Process Variations.
711-716
Electronic Edition (link) BibTeX
- Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov:
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
717-722
Electronic Edition (link) BibTeX
- Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
On Accelerating Soft-Error Detection by Targeted Pattern Generation.
723-728
Electronic Edition (link) BibTeX
- Edward Flanigan, Spyros Tragoudas:
Enhanced Identification of Strong Robustly Testable Paths.
729-736
Electronic Edition (link) BibTeX
Session 5C:
Variation Analysis and Design
- Zhuo Feng, Guo Yu, Peng Li:
Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction.
737-742
Electronic Edition (link) BibTeX
- Ning Lu, Judy H. McCullen:
Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance.
743-748
Electronic Edition (link) BibTeX
- Yang Liu, Tong Zhang, Jiang Hu:
Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.
749-754
Electronic Edition (link) BibTeX
- Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia:
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration.
755-760
Electronic Edition (link) BibTeX
- Ali Dasdan, Jinfeng Liu, Sridhar Tirumala, Kayhan Küçükçakar:
Designing and Validating Process-Variation-Aware Cell Libraries.
761-770
Electronic Edition (link) BibTeX
Session 5D:
Lithography and OPC
Session 6A:
DFM Process
- Subarna Sinha, Qing Su, Linni Wen, Frank Lee, Charles Chiang, Yi-Kan Cheng, Jin-Lien Lin, Yu-Chyi Harn:
A New Flexible Algorithm for Random Yield Improvement.
795-800
Electronic Edition (link) BibTeX
- Arthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud:
Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations.
801-806
Electronic Edition (link) BibTeX
- S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan:
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm.
807-813
Electronic Edition (link) BibTeX
- Shubhankar Basu, Priyanka Thakore, Ranga Vemuri:
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.
814-820
Electronic Edition (link) BibTeX
- Kevin W. McCullen:
Redundant Via Insertion in Restricted Topology Layouts.
821-828
Electronic Edition (link) BibTeX
Session 6B:
PDM Physical Planning
- Chen Li, Cheng-Kok Koh:
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement.
829-834
Electronic Edition (link) BibTeX
- Hongjie Bai, Sheqin Dong, Xianlong Hong:
Congestion Driven Buffer Planning for X-Architecture.
835-840
Electronic Edition (link) BibTeX
- Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages.
841-846
Electronic Edition (link) BibTeX
- Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong:
OPC-Friendly Bus Driven Floorplanning.
847-852
Electronic Edition (link) BibTeX
- Hailin Jiang, Malgorzata Marek-Sadowska:
Power-Gating Aware Floorplanning.
853-860
Electronic Edition (link) BibTeX
Session 6C:
Reliability and Interconnect at the System Level
- Frederic Worm, Patrick Thiran, Paolo Ienne:
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs.
861-866
Electronic Edition (link) BibTeX
- Praveen Bhojwani, Rabi N. Mahapatra:
An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs.
867-872
Electronic Edition (link) BibTeX
- Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud:
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations.
873-878
Electronic Edition (link) BibTeX
- Ting-Chun Huang, Ümit Y. Ogras, Radu Marculescu:
Virtual Channels Planning for Networks-on-Chip.
879-884
Electronic Edition (link) BibTeX
- Vyas Krishnan, Srinivas Katkoori:
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.
885-892
Electronic Edition (link) BibTeX
Session 6D:
Design and Modeling for Soft Error Reliability
- Natasa Miskov-Zivanov, Diana Marculescu:
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits.
893-898
Electronic Edition (link) BibTeX
- Liang Wang, Suge Yue, Yuanfu Zhao, Long Fan:
An SEU-Tolerant Programmable Frequency Divider.
899-904
Electronic Edition (link) BibTeX
- Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty:
A TMR Scheme for SEU Mitigation in Scan Flip-Flops.
905-910
Electronic Edition (link) BibTeX
- Krishnan Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Variation Impact on SER of Combinational Circuits.
911-916
Electronic Edition (link) BibTeX
- Christian J. Hescott, Drew C. Ness, David J. Lilja:
MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments.
917-922
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:26:16 2009
by Michael Ley (ley@uni-trier.de)
