| 2008 |
|---|
| 8 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Gate planning during placement for gated clock network.
ICCD 2008: 128-133 |
| 7 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong:
Leakage power optimization for clock network using dual-Vth technology.
ISCAS 2008: 2769-2772 |
| 6 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Activity and register placement aware gated clock network design.
ISPD 2008: 182-189 |
| 5 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Low Power Gated Clock Tree Driven Placement.
IEICE Transactions 91-A(2): 595-603 (2008) |
| 4 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu,
Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integration 41(3): 426-438 (2008) |
| 2007 |
|---|
| 3 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu,
Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
ISQED 2007: 299-304 |
| 2 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
ISVLSI 2007: 383-388 |
| 2006 |
|---|
| 1 | EE | Weixiang Shen,
Yici Cai,
Jiang Hu,
Xianlong Hong,
Bing Lu:
High performance clock routing in X-architecture.
ISCAS 2006 |
