2008 |
22 | EE | Zhuo Li,
Charles J. Alpert,
Shiyan Hu,
Tuhin Muhmud,
Stephen T. Quay,
Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment.
ISPD 2008: 71-77 |
2007 |
21 | EE | Shrirang K. Karandikar,
Charles J. Alpert,
Mehmet Can Yildiz,
Paul Villarrubia,
Stephen T. Quay,
T. Mahmud:
Fast Electrical Correction Using Resizing and Buffering.
ASP-DAC 2007: 553-558 |
20 | EE | Zhuo Li,
Charles J. Alpert,
Stephen T. Quay,
Sachin S. Sapatnekar,
Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages.
ISQED 2007: 841-846 |
19 | EE | Charles J. Alpert,
Shrirang K. Karandikar,
Zhuo Li,
Gi-Joon Nam,
Stephen T. Quay,
Haoxing Ren,
Cliff C. N. Sze,
Paul G. Villarrubia,
Mehmet Can Yildiz:
The nuts and bolts of physical synthesis.
SLIP 2007: 89-94 |
2004 |
18 | EE | Charles J. Alpert,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment.
DAC 2004: 24-29 |
17 | EE | Charles J. Alpert,
Milos Hrkic,
Stephen T. Quay:
A fast algorithm for identifying good buffer insertion candidate locations.
ISPD 2004: 47-52 |
16 | EE | Charles J. Alpert,
Chris C. N. Chu,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Chandramouli V. Kashyap,
Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004) |
15 | EE | Charles J. Alpert,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay,
Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004) |
2003 |
14 | EE | Charles J. Alpert,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay:
Porosity aware buffered steiner tree construction.
ISPD 2003: 158-165 |
13 | EE | Jiang Hu,
Charles J. Alpert,
Stephen T. Quay,
Gopal Gandham:
Buffer insertion with adaptive blockage avoidance.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 492-498 (2003) |
2002 |
12 | EE | Charles J. Alpert,
Chris C. N. Chu,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Chandramouli V. Kashyap,
Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
ISPD 2002: 104-109 |
11 | EE | Jiang Hu,
Charles J. Alpert,
Stephen T. Quay,
Gopal Gandham:
Buffer insertion with adaptive blockage avoidance.
ISPD 2002: 92-97 |
10 | EE | Charles J. Alpert,
Anirudh Devgan,
John P. Fishburn,
Stephen T. Quay:
Correction to "interconnect synthesis without wire tapering".
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 497-497 (2002) |
2001 |
9 | EE | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays.
ISCAS (5) 2001: 399-402 |
8 | EE | Charles J. Alpert,
Milos Hrkic,
Jiang Hu,
Andrew B. Kahng,
John Lillis,
Bao Liu,
Stephen T. Quay,
Sachin S. Sapatnekar,
A. J. Sullivan,
Paul Villarrubia:
Buffered Steiner trees for difficult instances.
ISPD 2001: 4-9 |
7 | EE | Charles J. Alpert,
Anirudh Devgan,
John P. Fishburn,
Stephen T. Quay:
Interconnect synthesis without wire tapering.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 90-104 (2001) |
6 | EE | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001) |
2000 |
5 | EE | José Luis Neves,
Stephen T. Quay:
Buffer Library Selection.
ICCD 2000: 221-226 |
1999 |
4 | EE | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Buffer Insertion with Accurate Gate and Interconnect Delay Computation.
DAC 1999: 479-484 |
3 | EE | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Is wire tapering worthwhile?
ICCAD 1999: 430-436 |
2 | EE | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Buffer insertion for noise and delay optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1633-1645 (1999) |
1998 |
1 | EE | Charles J. Alpert,
Anirudh Devgan,
Stephen T. Quay:
Buffer Insertion for Noise and Delay Optimization.
DAC 1998: 362-367 |