2009 | ||
---|---|---|
63 | EE | Yahya Jan, Lech Józwiak: Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. ARC 2009: 342-348 |
62 | EE | Lech Józwiak, Nadia Nedjah: Modern Architectures for Embedded Reconfigurable Systems - a Survey. Journal of Circuits, Systems, and Computers 18(2): 209-254 (2009) |
2008 | ||
61 | EE | Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk: High-Quality Circuit Synthesis for Modern Technologies. ISQED 2008: 168-173 |
60 | EE | Lech Józwiak, Alexander Douglas: Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. ITNG 2008: 1123-1130 |
59 | EE | Venkatesan Muthukumar, Lech Józwiak: Editorial. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 347-348 (2008) |
58 | EE | Lech Józwiak, Sien-An Ong: Quality-driven model-based architecture synthesis for real-time embedded SoCs. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 349-368 (2008) |
2007 | ||
57 | EE | Srikanth Venkataraman, Nagesh Nagapalli, Lech Józwiak: Quality Driven Manufacturing and SOC Designs. ISQED 2007: 5 |
56 | EE | Lech Józwiak: Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. ISQED 2007: 6 |
2006 | ||
55 | EE | Lech Józwiak: Life-Inspired Systems and Their Quality-Driven Design. ARCS 2006: 1-16 |
54 | EE | Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski: Multi-objective Optimal FSM State Assignment. DSD 2006: 385-396 |
53 | EE | Lech Józwiak, Sien-An Ong: Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. DSD 2006: 397-406 |
52 | EE | Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk: Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. ICSAMOS 2006: 177-184 |
2005 | ||
51 | EE | Lech Józwiak, Szymon Bieganski: High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. DSD 2005: 450-459 |
50 | EE | Lech Józwiak, Kaustav Banerjee: Plenary Session 2P. ISQED 2005: 461 |
49 | EE | Lech Józwiak: Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. IWSOC 2005: 139-142 |
48 | EE | Henry Selvaraj, Lech Józwiak: Reconfigurable embedded systems: Synthesis, design and application. Journal of Systems Architecture 51(6-7): 347-349 (2005) |
47 | EE | Lech Józwiak, Szymon Bieganski, Artur Chojnacki: Information-driven circuit synthesis with the pre-characterized gate libraries. Journal of Systems Architecture 51(6-7): 405-423 (2005) |
2004 | ||
46 | EE | Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk: An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. DSD 2004: 160-167 |
45 | EE | Lech Józwiak, Szymon Bieganski: Information Trans-Coders in Information-Driven Circuit Synthesis. DSD 2004: 288-397 |
44 | EE | Lech Józwiak: Life-Inspired Systems. DSD 2004: 36-43 |
43 | EE | Lech Józwiak, Aleksander Slusarczyk: General decomposition of incompletely specified sequential machines with multi-state behavior realization. Journal of Systems Architecture 50(8): 445-492 (2004) |
2003 | ||
42 | EE | Lech Józwiak, Szymon Bieganski, Artur Chojnacki: Information-driven Library-based Circuit Synthesis. DSD 2003: 148-157 |
41 | EE | Lech Józwiak: Advanced AI Search Techniques in Modern Digital Circuit Synthesis. Artif. Intell. Rev. 20(3-4): 269-318 (2003) |
40 | EE | Martyn Edwards, Lech Józwiak: Preface. Journal of Systems Architecture 49(12-15): 485-487 (2003) |
39 | EE | Martyn Edwards, Lech Józwiak: Special-issue on reconfigurable systems. Journal of Systems Architecture 49(4-6): 123-125 (2003) |
38 | EE | Lech Józwiak, Aleksander Slusarczyk, Artur Chojnacki: Fast and compact sequential circuits for the FPGA-based reconfigurable systems. Journal of Systems Architecture 49(4-6): 227-246 (2003) |
37 | EE | Lech Józwiak, Artur Chojnacki: Effective and efficient FPGA synthesis through general functional decomposition. Journal of Systems Architecture 49(4-6): 247-265 (2003) |
2002 | ||
36 | EE | Aleksander Slusarczyk, Lech Józwiak: Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. ISQED 2002: 87- |
35 | EE | Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak: Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach. IEEE Micro 22(3): 41-51 (2002) |
34 | EE | Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak: Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture. IEEE Micro 22(3): 52-61 (2002) |
33 | EE | Lech Józwiak, Adam Postula: Genetic engineering versus natural evolution: Genetic algorithms with deterministic operators. Journal of Systems Architecture 48(1-3): 99-112 (2002) |
2001 | ||
32 | EE | Lech Józwiak, Artur Chojnacki: High-quality sub-function construction in functional decomposition based on information relationship measures. DATE 2001: 383-390 |
31 | EE | Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola: Regular Realization of Symmetric Functions Using Reversible Logic. DSD 2001: 245-253 |
30 | EE | Lech Józwiak, Artur Chojnacki: Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. DSD 2001: 30-37 |
29 | EE | Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk: Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. DSD 2001: 46-53 |
28 | EE | Artur Chojnacki, Lech Józwiak: High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. ISQED 2001: 409-414 |
2000 | ||
27 | EE | Lech Józwiak, Aleksander Slusarczyk: A New State Assignment Method Targeting FPGA Implementations. EUROMICRO 2000: 1050-1059 |
26 | EE | Artur Chojnacki, Lech Józwiak: Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. ISMVL 2000: 83-90 |
25 | EE | Lech Józwiak: Quality-Driven System-on-a-Chip Design. ISQED 2000: 93- |
1999 | ||
24 | EE | Lech Józwiak: Digital System Design: Architectures, Methods and Tools. EUROMICRO 1999: 1004- |
23 | EE | Mariusz Rawski, Lech Józwiak, Tadeusz Luba: The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. EUROMICRO 1999: 1086-1093 |
22 | EE | Mariusz Rawski, Lech Józwiak, Tadeusz Luba: Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. EUROMICRO 1999: 1094-1101 |
21 | EE | Lech Józwiak, Artur Chojnacki: Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric Functions. EUROMICRO 1999: 1150-1160 |
20 | EE | Song Chen, Adam Postula, Lech Józwiak: Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention. EUROMICRO 1999: 1170-1177 |
19 | EE | Torrey Lewis, Marek A. Perkowski, Lech Józwiak: Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine. EUROMICRO 1999: 1326-1334 |
18 | EE | Rafal Rzechowski, Tadeusz Luba, Lech Józwiak: Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. EUROMICRO 1999: 1368-1375 |
17 | Lech Józwiak, Adam Postula: Genetic Engineering versus Natural Evolution Genetic Algorithms with Deterministic Operators. IC-AI 1999: 58-64 | |
16 | EE | Lech Józwiak: Information Relationships and Measures in Application to Logic Design. ISMVL 1999: 228-235 |
1998 | ||
15 | EE | Lech Józwiak, Niek Ederveen, Adam Postula: Solving Synthesis Problems with Genetic Algorithms. EUROMICRO 1998: 10001-10007 |
14 | EE | Mariusz Rawski, Tadeusz Luba, Lech Józwiak, Artur Chojnacki: Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. EUROMICRO 1998: 10008-10015 |
13 | EE | Michael Burns, Marek A. Perkowski, Lech Józwiak: An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables. EUROMICRO 1998: 10016-10023 |
12 | EE | Adam Postula, Song Chen, Lech Józwiak, David Abramson: Automated Synthesis of Interleaved Memory Systems for Custom Computing Machine. EUROMICRO 1998: 10115-10122 |
11 | EE | Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak: Design of Self-Synchronized Component FSMs for Self-Timed Systems. EUROMICRO 1998: 10253-10260 |
10 | EE | Mariusz Rawski, Lech Józwiak, Artur Chojnacki: Application of the Information Measures to Input Support Selection in Functional Decomposition. Rough Sets and Current Trends in Computing 1998: 573-580 |
9 | EE | Lech Józwiak: Analysis and Synthesis of Information Systems with Information Relationships and Measures. Rough Sets and Current Trends in Computing 1998: 585-588 |
1997 | ||
8 | EE | Lech Józwiak: Information Relationships and Measures An Analysis Apparatus for Efficient Information System Synthesis. EUROMICRO 1997: 13-23 |
7 | EE | Sien-An Ong, Kari Tiensyrjä, Lech Józwiak: Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models. EUROMICRO 1997: 172-181 |
6 | EE | Sanof Mohamed, Marek A. Perkowski, Lech Józwiak: Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures. EUROMICRO 1997: 31- |
5 | EE | Lech Józwiak: On the use of term trees for effective and efficient test pattern generation. EUROMICRO 1997: 87-95 |
4 | EE | Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang: Decomposition of Multiple-Valued Relations . ISMVL 1997: 13-18 |
3 | EE | Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak: Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL 1997: 287-292 |
1996 | ||
2 | EE | Lech Józwiak, Sien-An Ong: Quality-Driven Decision Making Methodology for System-Level Design. EUROMICRO 1996: 8-18 |
1990 | ||
1 | EE | Lech Józwiak: Efficent suboptimal state assignment for large sequential machines. EURO-DAC 1990: 536-541 |