| 2008 |
|---|
| 8 | EE | Takashi Sato,
Hiroyuki Ueyama,
Noriaki Nakayama,
Kazuya Masu:
Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
ASP-DAC 2008: 518-523 |
| 7 | EE | Masanori Imai,
Takashi Sato,
Noriaki Nakayama,
Kazuya Masu:
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
DAC 2008: 698-701 |
| 6 | EE | Masanori Imai,
Takashi Sato,
Noriaki Nakayama,
Kazuya Masu:
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis.
IEICE Transactions 91-A(4): 957-964 (2008) |
| 2007 |
|---|
| 5 | EE | Takashi Sato,
Takumi Uezono,
Shiho Hagiwara,
Kenichi Okada,
Shuhei Amakawa,
Noriaki Nakayama,
Kazuya Masu:
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.
ISQED 2007: 21-26 |
| 2005 |
|---|
| 4 | EE | Shizunori Matsumoto,
Hiroaki Ueno,
Satoshi Hosokawa,
Toshihiko Kitamura,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Tatsuya Ohguro,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Transactions 88-C(2): 247-254 (2005) |
| 3 | EE | Dondee Navarro,
Takeshi Mizoguchi,
Masami Suetake,
Kazuya Hisamitsu,
Hiroaki Ueno,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.
IEICE Transactions 88-C(5): 1079-1086 (2005) |
| 2002 |
|---|
| 2 | EE | Nobuyuki Sano,
Kazuya Matsuzawa,
Mikio Mukai,
Noriaki Nakayama:
On discrete random dopant modeling in drift-diffusion simulations: physical meaning of 'atomistic' dopants.
Microelectronics Reliability 42(2): 189-199 (2002) |
| 2001 |
|---|
| 1 | EE | D. Miyawaki,
Shizunori Matsumoto,
Hans Jürgen Mattausch,
S. Ooshiro,
Masami Suetake,
Michiko Miura-Mattausch,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
Correlation method of circuit-performance and technology fluctuations for improved design reliability.
ASP-DAC 2001: 39-44 |
