| 2007 |
|---|
| 10 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts.
ISQED 2007: 776-781 |
| 9 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization.
IEEE Trans. VLSI Syst. 15(6): 716-720 (2007) |
| 2006 |
|---|
| 8 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Timing-driven cell layout de-compaction for yield optimization by critical area minimization.
DATE 2006: 884-889 |
| 7 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells.
ISCAS 2006 |
| 2005 |
|---|
| 6 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact minimum-width transistor placement without dual constraint for CMOS cells.
ACM Great Lakes Symposium on VLSI 2005: 74-77 |
| 5 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells.
IEICE Transactions 88-A(12): 3485-3491 (2005) |
| 4 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization.
IEICE Transactions 88-A(7): 1957-1963 (2005) |
| 2004 |
|---|
| 3 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.
ASP-DAC 2004: 149-154 |
| 2 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.
ISQED 2004: 377-380 |
| 1998 |
|---|
| 1 | | Yuichi Iizuka,
Hisako Shiohara,
Tetsuya Iizuka,
Seiji Isobe:
Automatic Visualization Method for Visual Data Mining.
PAKDD 1998: 173-185 |
