| 2008 |
|---|
| 8 | EE | Young-Gu Kim,
Soo-Hwan Kim,
Hoon Lim,
Sanghoon Lee,
Keun-Ho Lee,
Young-Kwan Park,
Moon-Hyun Yoo:
The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era.
ISQED 2008: 369-372 |
| 2007 |
|---|
| 7 | EE | Jeong-Yeol Kim,
Ho-Soon Shin,
Jong-Bae Lee,
Moon-Hyun Yoo,
Jeong-Taek Kong:
SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design.
ISQED 2007: 475-480 |
| 2005 |
|---|
| 6 | EE | Yong-Chan Ban,
Soo-Han Choi,
Ki-Hung Lee,
Dong-Hyun Kim,
Ji-Suk Hong,
Yoo-Hyon Kim,
Moon-Hyun Yoo,
Jeong-Taek Kong:
A Fast Lithography Verification Framework for Litho-Friendly Layout Design.
ISQED 2005: 169-174 |
| 5 | EE | Young-Seok Hong,
Heeseok Lee,
Joon-Ho Choi,
Moon-Hyun Yoo,
Jeong-Taek Kong:
Analysis for Complex Power Distribution Networks Considering Densely Populated Vias.
ISQED 2005: 208-212 |
| 2004 |
|---|
| 4 | EE | Jong-Eun Koo,
Kyung-Ho Lee,
Young-Hoe Cheon,
Joon-Ho Choi,
Moon-Hyun Yoo,
Jeong-Taek Kong:
A Variable Reduction Technique for the Analysis of Ultra Large-Scale Power Distribution Networks.
ISQED 2004: 137-142 |
| 2003 |
|---|
| 3 | EE | Jae-Seok Yang,
Jeong-Yeol Kim,
Joon-Ho Choi,
Moon-Hyun Yoo,
Jeong-Taek Kong:
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis.
ISQED 2003: 344-347 |
| 2002 |
|---|
| 2 | EE | Chul-Hong Park,
Soo-Han Choi,
Sang-Uhk Rhie,
Dong-Hyun Kim,
Jun-Seong Park,
Tae-Hwang Jang,
Ji-Soong Park,
Yoo-Hyon Kim,
Moon-Hyun Yoo,
Jeong-Taek Kong:
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond.
ISQED 2002: 143-147 |
| 2000 |
|---|
| 1 | EE | Ji-Soong Park,
Chul-Hong Park,
Sang-Uhk Rhie,
Yoo-Hyon Kim,
Moon-Hyun Yoo,
Jeong-Taek Kong,
Hyung-Woo Kim,
Sun-Il Yoo:
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC.
ISQED 2000: 81-86 |
