| 2009 |
|---|
| 9 | EE | Brian Greskamp,
Lu Wan,
Ulya R. Karpuzcu,
Jeffrey J. Cook,
Josep Torrellas,
Deming Chen,
Craig B. Zilles:
Blueshift: Designing processors for timing speculation from the ground up.
HPCA 2009: 213-224 |
| 2008 |
|---|
| 8 | EE | Smruti R. Sarangi,
Brian Greskamp,
Abhishek Tiwari,
Josep Torrellas:
EVAL: Utilizing processors with variation-induced timing errors.
MICRO 2008: 423-434 |
| 2007 |
|---|
| 7 | EE | Brian Greskamp,
Smruti R. Sarangi,
Josep Torrellas:
Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates.
ISCAS 2007: 1261-1264 |
| 6 | EE | Smruti R. Sarangi,
Brian Greskamp,
Josep Torrellas:
A Model for Timing Errors in Processors with Parameter Variation.
ISQED 2007: 647-654 |
| 5 | EE | Brian Greskamp,
Josep Torrellas:
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking.
PACT 2007: 213-224 |
| 4 | EE | Cyrus Bazeghi,
Francisco J. Mesa-Martinez,
Brian Greskamp,
Josep Torrellas,
Jose Renau:
Estimating design time for system circuits.
VLSI-SoC 2007: 60-65 |
| 2006 |
|---|
| 3 | EE | Smruti R. Sarangi,
Brian Greskamp,
Josep Torrellas:
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging.
DSN 2006: 301-312 |
| 2 | EE | Ron Sass,
Brian Greskamp,
Brian Leonard,
Jeff Young,
Srinivas Beeravolu:
Online architectures: A theoretical formulation and experimental prototype.
Microprocessors and Microsystems 30(6): 319-333 (2006) |
| 2005 |
|---|
| 1 | EE | Brian Greskamp,
Ron Sass:
A Virtual Machine for Merit-Based Runtime Reconfiguration.
FCCM 2005: 287-288 |
