| 2008 |
|---|
| 18 | EE | Yu-Heng George Lee,
James Helton,
Chien-In Henry Chen:
Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver.
ISCAS 2008: 2494-2497 |
| 17 | EE | Kumar Yelamarthi,
Chien-In Henry Chen:
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.
ISQED 2008: 143-147 |
| 16 | EE | James Helton,
Chien-In Henry Chen,
David M. Lin,
James B. Y. Tsui:
FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver.
ISQED 2008: 568-571 |
| 15 | EE | Kumar Yelamarthi,
Chien-In Henry Chen:
Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.
JCP 3(2): 21-28 (2008) |
| 2007 |
|---|
| 14 | EE | Kumar Yelamarthi,
Chien-In Henry Chen:
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.
ISQED 2007: 426-431 |
| 2005 |
|---|
| 13 | EE | Shailesh Radhakrishnan,
Mingzhen Wang,
Chien-In Henry Chen:
A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder.
ISCAS (6) 2005: 6142-6145 |
| 2003 |
|---|
| 12 | EE | Chien-In Henry Chen,
Kiran George:
Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].
ISCAS (5) 2003: 521-524 |
| 11 | EE | Chien-In Henry Chen,
Kiran George:
Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.
ISQED 2003: 111- |
| 2001 |
|---|
| 10 | | Chien-In Henry Chen:
Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults.
ISSS 2001: 203-208 |
| 1999 |
|---|
| 9 | EE | Meghanad D. Wagh,
Chien-In Henry Chen:
High-level design synthesis with redundancy removal for high speed testable adders.
ISCAS (6) 1999: 358-361 |
| 1994 |
|---|
| 8 | | Chien-In Henry Chen,
Anup Kumar:
Comments on "Area-Time Optimal Adder Design".
IEEE Trans. Computers 43(4): 507-512 (1994) |
| 7 | EE | Chien-In Henry Chen,
Joel T. Yuen:
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design.
IEEE Trans. VLSI Syst. 2(3): 273-291 (1994) |
| 1993 |
|---|
| 6 | EE | Chien-In Henry Chen,
Joel T. Yuen:
Logic partitioning to pseudo-exhaustive test for BIST design.
ICCAD 1993: 646-649 |
| 1992 |
|---|
| 5 | | Chien-In Henry Chen,
Joel T. Yuen:
Concurrent Test Scheduling in Built-In Self-Test Environment.
ICCD 1992: 256-259 |
| 4 | | Chien-In Henry Chen,
Joel T. Yuen,
Ji-Der Lee:
Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment.
ICCD 1992: 264-267 |
| 1991 |
|---|
| 3 | EE | Chien-In Henry Chen:
Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit.
DAC 1991: 287-290 |
| 2 | | Chien-In Henry Chen:
BISTSYN - A Built-In Self-Test Synthesizer.
ICCAD 1991: 240-243 |
| 1 | | Chien-In Henry Chen:
Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis.
ICCD 1991: 418-421 |
