Hamid R. Zarandi

2007
19	EE	Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan: Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. DFT 2007: 340-348
18	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan: Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. IPDPS 2007: 1-6
17	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS 2007: 141-144
16	EE	Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan: Multiple Upsets Tolerance in SRAM Memory. ISCAS 2007: 365-368
15	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS 2007: 3675-3678
14	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan: CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. ISCAS 2007: 3696-3699
13	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED 2007: 380-385
12	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi: Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. Microelectronics Reliability 47(2-3): 461-470 (2007)
2006
11	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi: Hierarchical Set-Associate Cache for High-Performance and Low-Energy Architecture. Journal of Circuits, Systems, and Computers 15(6): 861-880 (2006)
10	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi: A fault-tolerant cache architecture based on binary set partitioning. Microelectronics Reliability 46(1): 86-99 (2006)
2005
9	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi: Hierarchical Multiple Associative Mapping in Cache Memories. ECBS 2005: 95-101
8	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi: Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme. LADC 2005: 121-130
2004
7		Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali: A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. ESA/VLSI 2004: 582-588
6	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad: Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. IOLTS 2004: 101-108
5	EE	Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali: Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. PRDC 2004: 327-332
4	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi: A Highly Fault Detectable Cache Architecture for Dependable Computing. SAFECOMP 2004: 45-59
2003
3	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali: Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. DFT 2003: 485-492
2	EE	Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi: A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. DSN 2003: 479-
1	EE	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali: Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. ISPDC 2003: 281-

Coauthor Index

1	Costas Argyrides	[14] [16] [18] [19]
2	Hossein Asadi (Ghazanfar Asadi)	[2] [5]
3	Alireza Ejlali (Ali Reza Ejlali)	[1] [2] [3] [5] [7]
4	Shaahin Hessabi	[7]
5	Jimson Mathew	[13] [15] [17]
6	Seyed Ghassem Miremadi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [17] [18]
7	Dhiraj K. Pradhan	[13] [14] [15] [16] [17] [18] [19]
8	Hamid Sarbazi-Azad	[6]
9	Siavash Bayat Sarmadi	[2]