Rajeev Murgai

2008
42	EE	Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng: Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE 2008: 537-540
2007
41	EE	Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng: Fast power network analysis with multiple clock domains. ICCD 2007: 456-463
40	EE	Gustavo R. Wilke, Rajeev Murgai: Design and Analysis of "Tree+Local Meshes" Clock Architecture. ISQED 2007: 165-170
39	EE	Vineet Wason, Rajeev Murgai, William W. Walker: An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. VLSI Design 2007: 271-277
2006
38	EE	Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai: Analyzing timing uncertainty in mesh-based clock architectures. DATE 2006: 1097-1102
37	EE	Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai: Clock Distribution Architectures: A Comparative Study. ISQED 2006: 85-91
36	EE	Subodh M. Reddy, Rajeev Murgai: Accurate Substrate Noise Analysis Based on Library Module Characterization. VLSI Design 2006: 355-362
2005
35		Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai: A sliding window scheme for accurate clock mesh analysis. ICCAD 2005: 939-946
34	EE	Rajeev Murgai: Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. VLSI Design 2005: 97-102
33	EE	Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury: ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 56-64 (2005)
2004
32	EE	Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori: Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. DATE 2004: 610-615
31	EE	Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury: Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. DATE 2004: 824-829
30	EE	Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma: XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. ICCD 2004: 208-215
29		Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury: Macromodeling of digital libraries for substrate noise analysis. ISCAS (5) 2004: 516-519
28	EE	Rajeev Murgai: Net Buffering in the Presence of Multiple Timing Views. VLSI Design 2004: 721-726
2003
27	EE	Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura: PDL: A New Physical Synthesis Methodology. ISQED 2003: 348-
26	EE	Arlindo L. Oliveira, Rajeev Murgai: On the problem of gate assignment under different rise and fall delays. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 807-814 (2003)
2002
25		Rajeev Murgai: Net Buffering in the Presence of Multiple Timing Views. IWLS 2002: 367-372
24	EE	Supratik Chakraborty, Rajeev Murgai: Layout-Driven Timing Optimization by Generalized De Morgan Transform. VLSI Design 2002: 647-654
2001
23	EE	Rajeev Murgai: Efficient global fanout optimization algorithms. ASP-DAC 2001: 571-576
22	EE	Supratik Chakraborty, Rajeev Murgai: Complexity Of Minimum-Delay Gate Resizing. VLSI Design 2001: 425-430
2000
21		Rajeev Murgai: Layout-Driven Area-Constrained Timing Optimization by Net Buffering. ICCAD 2000: 379-386
20		Arlindo L. Oliveira, Rajeev Murgai: An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. ICCAD 2000: 451-457
19	EE	Rajeev Murgai: Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. VLSI Design 2000: 240-
1999
18	EE	Rajeev Murgai, Masahiro Fujita: On Reducing Transitions Through Data Modifications. DATE 1999: 82-
17	EE	Rajeev Murgai: Performance optimization under rise and fall parameters. ICCAD 1999: 185-190
16	EE	Rajeev Murgai: On the global fanout optimization problem. ICCAD 1999: 511-515
15		Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita: Speeding Up Look-up-Table Driven Logic Simulation. VLSI 1999: 385-397
14	EE	Rajeev Murgai, Jawahar Jain, Masahiro Fujita: Efficient Scheduling Techniques for ROBDD Construction. VLSI Design 1999: 394-401
1998
13	EE	Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira: Using Complementation and Resequencing to Minimize Transitions. DAC 1998: 694-697
1997
12	EE	Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita: Speeding up technology-independent timing optimization by network partitioning. ICCAD 1997: 83-90
11	EE	Rajeev Murgai, Masahiro Fujita: Some Recent Advances in Software and Hardware Logic Simulation. VLSI Design 1997: 232-238
1995
10	EE	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose: Logic synthesis for a single large look-up table. ICCD 1995: 415-
1994
9	EE	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Optimum Functional Decomposition Using Encoding. DAC 1994: 408-414
1993
8	EE	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential Synthesis for Table Look Up Programmable Gate Arrays. DAC 1993: 224-229
7	EE	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Cube-packing and two-level minimization. ICCAD 1993: 115-122
6		Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. ICCD 1993: 505-512
1992
5	EE	Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: An Improved Synthesis Algorithm for Multiplexor-Based PGA's. DAC 1992: 380-386
1991
4		Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD 1991: 564-567
3		Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD 1991: 572-575
2		Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: On Clustering for Minimum Delay/Area. ICCAD 1991: 6-9
1990
1	EE	Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625

Coauthor Index

1	Rajat Aggarwal	[12]
2	Robert K. Brayton	[1] [2] [3] [4] [5] [6] [7] [8] [9]
3	Supratik Chakraborty	[22] [24]
4	Hongyu Chen	[35] [37]
5	Chung-Kuan Cheng	[41] [42]
6	Lew Chua-Eoan	[41] [42]
7	Kazuhiro Emi	[27]
8	Masahiro Fujita	[10] [11] [12] [13] [14] [15] [18]
9	Fumiyasu Hirose	[10] [15]
10	Takeshi Horie	[32]
11	Noriyuki Ito	[41]
12	Nuriyoki Ito	[42]
13	Jawahar Jain	[14]
14	Kaoru Kawamura	[27]
15	Tadashi Konno	[27]
16	Yinghua Li	[30]
17	Takashi Miyoshi	[30] [32] [37]
18	Hoa-van Nguyen	[35] [37]
19	Yoshihito Nishizaki	[1]
20	Arlindo L. Oliveira	[13] [20] [26]
21	He Peng	[41] [42]
22	Subodh M. Reddy	[32] [35] [36] [37] [38]
23	Jaijeet S. Roychowdhury	[29] [31] [33]
24	Alberto L. Sangiovanni-Vincentelli	[1] [2] [3] [4] [5] [6] [7] [8] [9]
25	Narendra V. Shenoy	[1] [3] [4]
26	Rui Shi	[41] [42]
27	Toshiyuki Shibuya	[27] [41] [42]
28	Mehdi Baradaran Tahoori	[32]
29	Ashwini Verma	[30]
30	William W. Walker	[35] [37] [39]
31	Zhe Wang	[29] [31] [33]
32	Vineet Wason	[39]
33	Gustavo R. Wilke	[35] [37] [38] [40]
34	Chao-Yang Yeh	[35] [37]
35	Wenjian Yu	[42]
36	Ling Zhang	[41] [42]
37	Wanping Zhang	[41] [42]
38	Yi Zhu	[42]
39	Zhi Zhu	[41] [42]

Colors in the list of coauthors