| |
| 2009 | ||
|---|---|---|
| 6 | EE | Vyas Krishnan, Srinivas Katkoori: Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis. VLSI Design 2009: 419-424 |
| 2008 | ||
| 5 | EE | Vyas Krishnan, Srinivas Katkoori: Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis. VLSI Design 2008: 641-646 |
| 2007 | ||
| 4 | EE | Vyas Krishnan, Srinivas Katkoori: A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. ISQED 2007: 885-892 |
| 3 | EE | Vyas Krishnan, Srinivas Katkoori: Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. VLSI-SoC 2007: 99-104 |
| 2006 | ||
| 2 | EE | Vyas Krishnan, Srinivas Katkoori: Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation. ISQED 2006: 364-369 |
| 1 | EE | Vyas Krishnan, Srinivas Katkoori: A genetic algorithm for the design space exploration of datapaths during high-level synthesis. IEEE Trans. Evolutionary Computation 10(3): 213-229 (2006) |
| 1 | Srinivas Katkoori | [1] [2] [3] [4] [5] [6] |