2008 |
30 | EE | Susumu Sadoshima,
Satoshi Fukuda,
Tackya Yammouch,
Hiroyuki Ito,
Kenichi Okada,
Kazuya Masu:
Small-area CMOS RF distributed mixer using multi-port inductors.
ASP-DAC 2008: 105-106 |
29 | EE | Takashi Sato,
Hiroyuki Ueyama,
Noriaki Nakayama,
Kazuya Masu:
Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
ASP-DAC 2008: 518-523 |
28 | EE | Akiko Mineyama,
Hiroyuki Ito,
Takahiro Ishii,
Kenichi Okada,
Kazuya Masu:
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.
ASP-DAC 2008: 97-98 |
27 | EE | Masanori Imai,
Takashi Sato,
Noriaki Nakayama,
Kazuya Masu:
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
DAC 2008: 698-701 |
26 | EE | Shiho Hagiwara,
Takumi Uezono,
Takashi Sato,
Kazuya Masu:
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network.
IEICE Transactions 91-A(4): 951-956 (2008) |
25 | EE | Masanori Imai,
Takashi Sato,
Noriaki Nakayama,
Kazuya Masu:
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis.
IEICE Transactions 91-A(4): 957-964 (2008) |
24 | EE | Kazuya Masu,
Kenichi Okada:
Reconfigurable RF CMOS Circuit for Cognitive Radio.
IEICE Transactions 91-B(1): 10-13 (2008) |
2007 |
23 | EE | Shiho Hagiwara,
Takumi Uezono,
Takashi Sato,
Kazuya Masu:
Improvement of power distribution network using correlation-based regression analysis.
ACM Great Lakes Symposium on VLSI 2007: 513-516 |
22 | EE | Satoshi Fukuda,
D. Kawazoe,
Kenichi Okada,
Kazuya Masu:
Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation.
ASP-DAC 2007: 104-105 |
21 | EE | Junki Seita,
Hiroyuki Ito,
Kenichi Okada,
Takashi Sato,
Kazuya Masu:
A Multi-Drop Transmission-Line Interconnect in Si LSI.
ASP-DAC 2007: 118-119 |
20 | EE | K. Ohashi,
Y. Ito,
Yoshiaki Yoshihara,
Kenichi Okada,
Kazuya Masu:
A Wideband CMOS LC-VCO Using Variable Inductor.
ASP-DAC 2007: 98-99 |
19 | EE | Takashi Sato,
Takumi Uezono,
Shiho Hagiwara,
Kenichi Okada,
Shuhei Amakawa,
Noriaki Nakayama,
Kazuya Masu:
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.
ISQED 2007: 21-26 |
18 | EE | Takashi Sato,
Shiho Hagiwara,
Takumi Uezono,
Kazuya Masu:
Weakness Identification for Effective Repair of Power Distribution Network.
PATMOS 2007: 222-231 |
17 | EE | Shuhei Amakawa,
Takumi Uezono,
Takashi Sato,
Kenichi Okada,
Kazuya Masu:
Adaptable wire-length distribution with tunable occupation probability.
SLIP 2007: 1-8 |
16 | EE | Hiroyuki Ito,
Hideyuki Sugita,
Kenichi Okada,
Tatsuya Ito,
Kazuhisa Itoi,
Masakazu Sato,
Ryozo Yamauchi,
Kazuya Masu:
Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology.
IEICE Transactions 90-C(3): 641-643 (2007) |
2006 |
15 | EE | D. Kawazoe,
Hirotaka Sugawara,
Tatsuya Ito,
Kenichi Okada,
Kazuya Masu:
Reconfigurable CMOS low noise amplifier for self compensation.
ISCAS 2006 |
14 | EE | Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Via Distribution Model for Yield Estimation.
ISQED 2006: 479-484 |
13 | EE | Kenichi Okada,
Takumi Uezono,
Kazuya Masu:
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.
PATMOS 2006: 181-190 |
12 | EE | Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Statistical Modeling of a Via Distribution for Yield Estimation.
IEICE Transactions 89-A(12): 3579-3584 (2006) |
11 | EE | Kazuya Masu,
Kenichi Okada,
Hiroyuki Ito:
RF Passive Components Using Metal Line on Si CMOS.
IEICE Transactions 89-C(6): 681-691 (2006) |
2005 |
10 | EE | Junpei Inoue,
Hiroyuki Ito,
Shinichiro Gomi,
Takanori Kyogoku,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Evaluation of on-chip transmission line interconnect using wire length distribution.
ASP-DAC 2005: 133-138 |
9 | EE | Kenichi Okada,
Yoshiaki Yoshihara,
Hirotaka Sugawara,
Kazuya Masu:
A dynamic reconfigurable RF circuit architecture.
ASP-DAC 2005: 683-686 |
8 | EE | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model Considering Core Utilization for System on Chip.
ISVLSI 2005: 276-277 |
7 | EE | Takumi Uezono,
Junpei Inoue,
Takanori Kyogoku,
Kenichi Okada,
Kazuya Masu:
Prediction of delay time for future LSI using on-chip transmission line interconnects.
SLIP 2005: 7-12 |
6 | EE | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.
IEICE Transactions 88-A(12): 3358-3366 (2005) |
5 | EE | Hidenari Nakashima,
Naohiro Takagi,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Evaluation of X Architecture Using Interconnect Length Distribution.
IEICE Transactions 88-A(12): 3437-3444 (2005) |
4 | EE | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model for System LSI.
IEICE Transactions 88-A(12): 3445-3452 (2005) |
3 | EE | Yoshiaki Yoshihara,
Hirotaka Sugawara,
Hiroyuki Ito,
Kenichi Okada,
Kazuya Masu:
Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit.
IEICE Transactions 88-A(2): 507-512 (2005) |
2004 |
2 | EE | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
ULSI Interconnect Length Distribution Model Considering Core Utilization.
DATE 2004: 1210-1217 |
1 | EE | Yoshiaki Yoshihara,
Hirotaka Sugawara,
Hiroyuki Ito,
Kenichi Okada,
Kazuya Masu:
Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design.
IEICE Electronic Express 1(7): 156-159 (2004) |