| 2009 |
|---|
| 61 | EE | MyeongGyu Jeong,
Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.
ACM Great Lakes Symposium on VLSI 2009: 177-180 |
| 2008 |
|---|
| 60 | EE | Makoto Ikeda,
Giuseppe De Marco,
Leonard Barolli,
Makoto Takizawa:
A BAT in the Lab: Experimental Results of New Link State Routing Protocol.
AINA 2008: 295-302 |
| 59 | EE | Tao Yang,
Makoto Ikeda,
Giuseppe De Marco,
Leonard Barolli,
Arjan Durresi,
Fatos Xhafa:
Routing Efficiency of AODV and DSR Protocols in Ad-Hoc Sensor Networks.
ICDCS Workshops 2008: 66-71 |
| 58 | EE | Leonard Barolli,
Tao Yang,
Makoto Ikeda,
Arjan Durresi,
Fatos Xhafa:
A Simulation System for Routing Efficiency in Wireless Sensor-Actor Networks: A Case Study for Semi-automated Architecture.
ICPADS 2008: 567-574 |
| 57 | EE | Makoto Ikeda,
Leonard Barolli,
Giuseppe De Marco,
Tao Yang,
Arjan Durresi:
Experimental and Simulation Evaluation of OLSR Protocol for Mobile Ad-Hoc Networks.
NBiS 2008: 111-121 |
| 56 | EE | Leonard Barolli,
Makoto Ikeda,
Arjan Durresi,
Fatos Xhafa,
Akio Koyama:
Performance Evaluation of Two Search Space Reduction Methods for a Distributed Network Architecture.
NBiS 2008: 49-59 |
| 55 | EE | Makoto Ikeda,
Giuseppe De Marco,
Tao Yang,
Leonard Barolli:
Performance analysis of an ad hoc network for emergency and collaborative environments.
Telecommunication Systems 38(3-4): 133-146 (2008) |
| 2007 |
|---|
| 54 | EE | Giuseppe De Marco,
Makoto Ikeda,
Tao Yang,
Leonard Barolli:
Experimental Performance Evaluation of a Pro-Active Ad-hoc Routing Protocol in Out- and Indoor Scenarios.
AINA 2007: 7-14 |
| 53 | EE | Taisuke Kazama,
Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Design of Active Substrate Noise Canceller using Power Supply di/dt Detector.
ASP-DAC 2007: 100-101 |
| 52 | EE | Leonard Barolli,
Makoto Ikeda,
Arjan Durresi,
Fatos Xhafa,
Akio Koyama:
A Distributed QoS Routing and CAC Framework: Performance Evaluation of Its SSRA and InterD Agents.
CISIS 2007: 60-67 |
| 51 | | Zhicheng Liang,
Makoto Ikeda,
Kunihiro Asada:
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology.
DDECS 2007: 81-86 |
| 50 | EE | Tao Yang,
Leonard Barolli,
Makoto Ikeda,
Arjan Durresi,
Fatos Xhafa:
Network energy consumption in ad-hoc networks under different radio models.
ICPADS 2007: 1-8 |
| 49 | EE | Tao Yang,
Makoto Ikeda,
Giuseppe De Marco,
Leonard Barolli:
Performance Behavior of AODV, DSR and DSDV Protocols for Different Radio Models in Ad-Hoc Sensor Networks.
ICPP Workshops 2007: 6 |
| 48 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts.
ISQED 2007: 776-781 |
| 47 | EE | Makoto Ikeda,
Giuseppe De Marco,
Leonard Barolli:
A Simple Statistical Methodology for Testing Ad Hoc Networks.
NBiS 2007: 1-10 |
| 46 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization.
IEEE Trans. VLSI Syst. 15(6): 716-720 (2007) |
| 45 | EE | Leonard Barolli,
Makoto Ikeda,
Giuseppe De Marco,
Arjan Durresi,
Akio Koyama,
Jiro Iwashige:
A Search Space Reduction Algorithm for Improving the Performance of a GA-based QoS Routing Method in Ad-Hoc Networks.
IJDSN 3(1): 41-57 (2007) |
| 44 | EE | Tao Yang,
Leonard Barolli,
Makoto Ikeda,
Arjan Durresi,
Fatos Xhafa:
Performance Evaluation of Reactive and Proactive Protocols for Ad-Hoc Sensor Networks Using Different Radio Models.
Journal of Interconnection Networks 8(4): 387-405 (2007) |
| 43 | EE | Giuseppe De Marco,
Tao Yang,
Makoto Ikeda,
Leonard Barolli:
Performance evaluation of wireless sensor networks for event-detection with shadowing-induced radio irregularities.
Mobile Information Systems 3(3-4): 251-266 (2007) |
| 2006 |
|---|
| 42 | EE | Mohamed Abbas,
Makoto Ikeda,
Kunihiro Asada:
On-chip 8GHz non-periodic high-swing noise detector.
DATE 2006: 670-671 |
| 41 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Timing-driven cell layout de-compaction for yield optimization by critical area minimization.
DATE 2006: 884-889 |
| 40 | | Mohamed Abbas,
Makoto Ikeda,
Kunihiro Asada:
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow.
DDECS 2006: 147-148 |
| 39 | EE | Makoto Ikeda,
Leonard Barolli,
Giuseppe De Marco,
Arjan Durresi,
Akio Koyama,
Mimoza Durresi:
Evaluation of a Network Extraction Topology Algorithm for Reducing Search Space of a GA-based Routing Approach.
ICDCS Workshops 2006: 54 |
| 38 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells.
ISCAS 2006 |
| 37 | | Tao Yang,
Giuseppe De Marco,
Makoto Ikeda,
Leonard Barolli:
A Case Study of Event Detection in Lattice Wireless Sensor Network with Shadowing-Induced Radio Irregularities.
MoMM 2006: 241-250 |
| 36 | EE | Hiroaki Yoshida,
Makoto Ikeda,
Kunihiro Asada:
A Structural Approach for Transistor Circuit Synthesis.
IEICE Transactions 89-A(12): 3529-3537 (2006) |
| 35 | EE | Taisuke Kazama,
Makoto Ikeda,
Kunihiro Asada:
LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil.
IEICE Transactions 89-A(12): 3546-3550 (2006) |
| 34 | EE | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Autonomous di/dt Control of Power Supply for Margin Aware Operation.
IEICE Transactions 89-C(11): 1689-1694 (2006) |
| 33 | EE | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply.
IEICE Transactions 89-C(3): 364-369 (2006) |
| 32 | EE | Mohamed Abbas,
Makoto Ikeda,
Kunihiro Asada:
On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function.
IEICE Transactions 89-C(3): 370-376 (2006) |
| 31 | EE | Mohamed Abbas,
Makoto Ikeda,
Kunihiro Asada:
Noise Immunity Investigation of Low Power Design Schemes.
IEICE Transactions 89-C(8): 1238-1247 (2006) |
| 30 | EE | Makoto Ikeda,
Leonard Barolli,
Akio Koyama,
Arjan Durresi,
Giuseppe De Marco,
Jiro Iwashige:
Performance evaluation of an intelligent CAC and routing framework for multimedia applications in broadband networks.
J. Comput. Syst. Sci. 72(7): 1183-1200 (2006) |
| 29 | EE | Tao Yang,
Giuseppe De Marco,
Makoto Ikeda,
Leonard Barolli:
Impact of radio randomness on performances of lattice wireless sensors networks based on event-reliability concept.
Mobile Information Systems 2(4): 211-227 (2006) |
| 2005 |
|---|
| 28 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact minimum-width transistor placement without dual constraint for CMOS cells.
ACM Great Lakes Symposium on VLSI 2005: 74-77 |
| 27 | EE | Yusuke Yachide,
Yusuke Oike,
Makoto Ikeda,
Kunihiro Asada:
Real-time 3-D measurement system based on light-section method using smart image sensor.
ICIP (3) 2005: 1008-1111 |
| 26 | EE | Makoto Ikeda,
Leonard Barolli,
Shohei Ohba,
Genci Capi,
Akio Koyama,
Mimoza Durresi:
A CAC and Routing Framework for Multimedia Applications in Broadband Networks Using Fuzzy Logic and Genetic Algorithm.
ICPADS (1) 2005: 648-654 |
| 25 | EE | Shohei Ohba,
Makoto Ikeda,
Leonard Barolli,
Giuseppe De Marco,
Jiro Iwashige,
Arjan Durresi:
An Effective Topology Extraction Algorithm for Search Reduction Space of a GA-based QoS Routing Method in Ad-Hoc Networks.
ISPAN 2005: 400-405 |
| 24 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells.
IEICE Transactions 88-A(12): 3485-3491 (2005) |
| 23 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization.
IEICE Transactions 88-A(7): 1957-1963 (2005) |
| 22 | EE | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Stub vs. Capacitor for Power Supply Noise Reduction.
IEICE Transactions 88-C(1): 125-132 (2005) |
| 21 | EE | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
On-chip di/dt Detector Circuit.
IEICE Transactions 88-C(5): 782-787 (2005) |
| 20 | EE | Toru Nakura,
Makoto Ikeda,
Kunihiro Asada:
Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs.
IEICE Transactions 88-C(8): 1734-1739 (2005) |
| 19 | EE | Ulkuhan Ekinciel,
Hiroaki Yamaoka,
Hiroaki Yoshida,
Makoto Ikeda,
Kunihiro Asada:
A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells.
IEICE Transactions 88-D(6): 1159-1167 (2005) |
| 2004 |
|---|
| 18 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.
ASP-DAC 2004: 149-154 |
| 17 | EE | Yusuke Oike,
Makoto Ikeda,
Kunihiro Asada:
Design of real-time VGA 3-D image sensor using mixed-signal techniques.
ASP-DAC 2004: 523-524 |
| 16 | EE | Mohamed Abbas,
Makoto Ikeda,
Kunihiro Asada:
Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime.
DFT 2004: 87-95 |
| 15 | EE | Tetsuya Iizuka,
Makoto Ikeda,
Kunihiro Asada:
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.
ISQED 2004: 377-380 |
| 2003 |
|---|
| 14 | EE | Yusuke Oike,
Makoto Ikeda,
Kunihiro Asada:
High-speed position detector using new row-parallel architecture for fast collision prevention system.
ISCAS (4) 2003: 788-791 |
| 13 | EE | Tohru Ishihara,
Satoshi Komatsu,
Makoto Ikeda,
Masahiro Fujita,
Kunihiro Asada:
Comparative Study On Verilog-Based And C-Based Hardware Design Education.
MSE 2003: 41-42 |
| 2002 |
|---|
| 12 | EE | Hiroaki Yoshida,
Hiroaki Yamaoka,
Makoto Ikeda,
Kunihiro Asada:
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.
VLSI Design 2002: 166-171 |
| 2001 |
|---|
| 11 | EE | Tomohiro Nezuka,
Masashi Hoshino,
Makoto Ikeda,
Kunihiro Asada:
A smart position sensor for 3-D measurement.
ASP-DAC 2001: 21-22 |
| 10 | EE | Jian Qiao,
Makoto Ikeda,
Kunihiro Asada:
Finding an optimal functional decomposition for LUT-based FPGA synthesis.
ASP-DAC 2001: 225-230 |
| 9 | EE | Hiroaki Yamaoka,
Makoto Ikeda,
Kunihiro Asada:
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.
ASP-DAC 2001: 3-4 |
| 8 | EE | Yusuke Nakashima,
Makoto Ikeda,
Kunihiro Asada:
Computational Cost Reduction in Extracting Inductance.
ISQED 2001: 179-184 |
| 2000 |
|---|
| 7 | EE | Tomohiro Nezuka,
Takafumi Fujita,
Makoto Ikeda,
Kunihiro Asada:
A binary image sensor with flexible motion vector detection using block matching method.
ASP-DAC 2000: 21-22 |
| 6 | EE | Jian Qiao,
Makoto Ikeda,
Kunihiro Asada:
Optimum Functional Decomposition for LUT-Based FPGA Synthesis.
FPL 2000: 555-564 |
| 5 | EE | Makoto Ikeda,
Hideyuki Aoki,
Kunihiro Asada:
DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path.
ISQED 2000: 305-308 |
| 1999 |
|---|
| 4 | EE | Satoshi Komatsu,
Makoto Ikeda,
Kunihiro Asada:
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method.
Great Lakes Symposium on VLSI 1999: 368-371 |
| 3 | EE | Makoto Ikeda,
Kunihiro Asada:
Standard design flows of Logic LSIs in Japanese universities and VDEC.
MSE 1999: 8-9 |
| 1998 |
|---|
| 2 | | Satoshi Komatsu,
Makoto Ikeda,
Kunihiro Asada:
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture.
ASP-DAC 1998: 323-324 |
| 1994 |
|---|
| 1 | | Makoto Ikeda,
Kunihiro Asada:
A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs.
EDAC-ETC-EUROASIC 1994: 546-550 |
