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Somnath Paul

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2008
14EESomnath Paul, Swarup Bhunia: MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. ASP-DAC 2008: 77-82
13EESeetharam Narasimhan, Somnath Paul, Swarup Bhunia: Collective computing based on swarm intelligence. DAC 2008: 349-350
12EESomnath Paul, Swarup Bhunia: Reconfigurable computing using content addressable memory for improved performance and resource usage. DAC 2008: 786-791
11EEYu Zhou, Somnath Paul, Swarup Bhunia: Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. DATE 2008: 98-103
10EERajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia: On-Demand Transparency for Improving Hardware Trojan Detectability. HOST 2008: 48-50
9EESomnath Paul, Saibal Mukhopadhyay, Swarup Bhunia: Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. ICCAD 2008: 589-592
8EEYu Zhou, Somnath Paul, Swarup Bhunia: Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. ISQED 2008: 861-866
7EERajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia: Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. VLSI Design 2008: 441-446
2007
6EESomnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia: Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404
5EESomnath Paul, Swarup Bhunia: Memory based computation using embedded cache for processor yield and reliability improvement. ICCD 2007: 341-346
4EESomnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia: Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. IOLTS 2007: 29-36
3EESivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia: Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. ISQED 2007: 755-760
2EESomnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia: VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. VTS 2007: 455-460
1998
1EEPradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta: Hardware/Software Co-design of a High-end Mixed Signal Microcontroller. VLSI Design 1998: 91-96

Coauthor Index

1Swarup Bhunia [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
2Rajat Subhra Chakraborty [2] [4] [7] [10]
3Rajat Gupta [1]
4Sivasubramaniam Krishnamurthy [3] [6]
5Hamid Mahmoodi (Hamid Mahmoodi-Meimand) [6]
6Pradeep K. Mishra [1]
7Saibal Mukhopadhyay [9]
8Seetharam Narasimhan [13]
9S. Venkataraman [1]
10Yu Zhou [8] [11]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)