2009 |
45 | EE | Hariharan Sankaran,
Srinivas Katkoori:
On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs.
ISQED 2009: 33-39 |
44 | EE | Vyas Krishnan,
Srinivas Katkoori:
Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis.
VLSI Design 2009: 419-424 |
2008 |
43 | EE | Hariharan Sankaran,
Srinivas Katkoori:
Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.
DELTA 2008: 454-457 |
42 | EE | Didier Keymeulen,
Adrian Stoica,
Ricardo Salem Zebulum,
Srinivas Katkoori,
Pradeep Fernando,
Hariharan Sankaran,
Mohammad Mojarradi,
Taher Daud:
Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.
ICES 2008: 225-236 |
41 | EE | Pradeep Fernando,
Hariharan Sankaran,
Srinivas Katkoori,
Didier Keymeulen,
Adrian Stoica,
Ricardo Salem Zebulum,
Rajeshuni Ramesham:
A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.
IPDPS 2008: 1-8 |
40 | EE | Hariharan Sankaran,
Srinivas Katkoori:
Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis.
ISVLSI 2008: 423-428 |
39 | EE | Pradeep Fernando,
Srinivas Katkoori:
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.
VLSI Design 2008: 337-342 |
38 | EE | Vyas Krishnan,
Srinivas Katkoori:
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.
VLSI Design 2008: 641-646 |
2007 |
37 | EE | Adrian Stoica,
Didier Keymeulen,
Ricardo Salem Zebulum,
Mohammad Mojarradi,
Srinivas Katkoori,
Taher Daud:
Adaptive and Evolvable Analog Electronics for Space Applications.
ICES 2007: 379-390 |
36 | EE | Vyas Krishnan,
Srinivas Katkoori:
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.
ISQED 2007: 885-892 |
35 | EE | Soumyaroop Roy,
Srinivas Katkoori,
Nagarajan Ranganathan:
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors.
VLSI Design 2007: 215-220 |
34 | EE | Vyas Krishnan,
Srinivas Katkoori:
Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.
VLSI-SoC 2007: 99-104 |
2006 |
33 | EE | Adrian Stoica,
Ricardo Salem Zebulum,
Didier Keymeulen,
Rajeshuni Ramesham,
Joseph Neff,
Srinivas Katkoori:
Temperature-Adaptive Circuits on Reconfigurable Analog Arrays.
AHS 2006: 28-31 |
32 | EE | Didier Keymeulen,
Ricardo Salem Zebulum,
Rajeshuni Ramesham,
Adrian Stoica,
Srinivas Katkoori,
Sharon Graves,
Frank Novak,
Charles Antill:
Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics.
AHS 2006: 296-300 |
31 | EE | Vyas Krishnan,
Srinivas Katkoori:
Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.
ISQED 2006: 364-369 |
30 | EE | Vyas Krishnan,
Srinivas Katkoori:
A genetic algorithm for the design space exploration of datapaths during high-level synthesis.
IEEE Trans. Evolutionary Computation 10(3): 213-229 (2006) |
2005 |
29 | EE | Ranganath Gopalan,
Chandramouli Gopalakrishnan,
Srinivas Katkoori:
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths.
ISVLSI 2005: 167-172 |
28 | EE | Hariharan Sankaran,
Srinivas Katkoori,
Umadevi Kailasam:
System Level Energy Optimization for Location Aware Computing.
PerCom 2005: 319-323 |
27 | EE | Suvodeep Gupta,
Srinivas Katkoori,
Hariharan Sankaran:
Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs.
VLSI Design 2005: 463-468 |
26 | EE | Suvodeep Gupta,
Srinivas Katkoori:
Intrabus crosstalk estimation using word-level statistics.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 469-478 (2005) |
2004 |
25 | EE | Suvodeep Gupta,
Srinivas Katkoori:
A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk.
DATE 2004: 1110-1115 |
24 | EE | Hao Li,
Wai-Kei Mak,
Srinivas Katkoori:
Force-Directed Performance-Driven Placement Algorithm for FPGAs.
ISVLSI 2004: 193-198 |
23 | EE | Chandramouli Gopalakrishnan,
Srinivas Katkoori:
Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths.
ISVLSI 2004: 260-261 |
22 | EE | Suvodeep Gupta,
Srinivas Katkoori:
Intra-Bus Crosstalk Estimation Using Word-Level Statistics.
VLSI Design 2004: 449-454 |
21 | EE | Stelian Alupoaei,
Srinivas Katkoori:
Energy Model Based Macrocell Placement for Wirelength Minimization.
VLSI Design 2004: 713-716 |
20 | EE | Stelian Alupoaei,
Srinivas Katkoori:
Ant Colony Optimization Technique for Macrocell Overlap Removal.
VLSI Design 2004: 963-968 |
19 | EE | Hao Li,
Srinivas Katkoori,
Wai-Kei Mak:
Power minimization algorithms for LUT-based FPGA technology mapping.
ACM Trans. Design Autom. Electr. Syst. 9(1): 33-51 (2004) |
18 | EE | Stelian Alupoaei,
Srinivas Katkoori:
Ant colony system application to macrocell overlap removal.
IEEE Trans. VLSI Syst. 12(10): 1118-1123 (2004) |
17 | EE | Stelian Alupoaei,
Srinivas Katkoori:
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement.
VLSI Signal Processing 37(1): 151-163 (2004) |
2003 |
16 | EE | Chandramouli Gopalakrishnan,
Srinivas Katkoori:
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths.
ICCD 2003: 430-435 |
15 | EE | Chandramouli Gopalakrishnan,
Srinivas Katkoori:
An Architectural Leakage Power Simulator for VHDL Structural Datapaths.
ISVLSI 2003: 211-212 |
14 | EE | Chandramouli Gopalakrishnan,
Srinivas Katkoori:
Resource Allocation and Binding Approach for Low Leakage Power.
VLSI Design 2003: 297-302 |
2002 |
13 | EE | Chandramouli Gopalakrishnan,
Srinivas Katkoori:
Power Optimization of Combinational Circuits by Input Transformations.
DELTA 2002: 154-158 |
12 | EE | Chandramouli Gopalakrishnan,
Srinivas Katkoori:
Behavioral synthesis of datapaths with low leakage power.
ISCAS (4) 2002: 699-702 |
11 | EE | Suvodeep Gupta,
Srinivas Katkoori:
Force-Directed Scheduling for Dynamic Power Optimization.
ISVLSI 2002: 75-82 |
10 | EE | Stelian Alupoaei,
Srinivas Katkoori:
Net Clustering Based Macrocell Placement.
VLSI Design 2002: 399- |
9 | EE | Ranga Vemuri,
Srinivas Katkoori,
Meenakshi Kaul,
Jay Roy:
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.
ACM Trans. Design Autom. Electr. Syst. 7(1): 189-216 (2002) |
8 | EE | Stelian Alupoaei,
Srinivas Katkoori:
Net-based force-directed macrocell placement for wirelength optimization.
IEEE Trans. VLSI Syst. 10(6): 824-835 (2002) |
1999 |
7 | EE | Srinivas Katkoori,
Ranga Vemuri:
Accurate Resource Estimation Algorithms for Behavioral Synthesis.
Great Lakes Symposium on VLSI 1999: 338-339 |
6 | | Ananth Durbha,
Srinivas Katkoori:
RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime.
VLSI 1999: 427-438 |
1996 |
5 | EE | Srinivas Katkoori,
Ranga Vemuri:
Simulation based architectural power estimation for PLA-based controllers.
ISLPED 1996: 121-124 |
4 | EE | Srinivas Katkoori,
Ranga Vemuri,
Jay Roy:
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis.
VLSI Design 1996: 126-132 |
1995 |
3 | EE | Srinivas Katkoori,
Nand Kumar,
Ranga Vemuri:
High level profiling based low power synthesis technique.
ICCD 1995: 446- |
2 | EE | Nand Kumar,
Srinivas Katkoori,
Leo Rader,
Ranga Vemuri:
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems.
IEEE Design & Test of Computers 12(3): 70-84 (1995) |
1994 |
1 | | Dinesh Bhatia,
Ramesh Rajagopalan,
Srinivas Katkoori:
Hierarchical Reconfiguration of VLSI/WSI Arrays.
VLSI Design 1994: 349-352 |