| 2007 |
|---|
| 11 | EE | Minh Quang Do,
Mindaugas Drazdziulis,
Per Larsson-Edefors,
Lars Bengtsson:
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
ISQED 2007: 185-191 |
| 10 | EE | Björn Nilsson,
Lars Bengtsson,
Per-Arne Wiberg,
Bertil Svensson:
Protocols for Active RFID - The Energy Consumption Aspect.
SIES 2007: 41-48 |
| 2006 |
|---|
| 9 | EE | Minh Quang Do,
Mindaugas Drazdziulis,
Per Larsson-Edefors,
Lars Bengtsson:
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.
ISQED 2006: 557-563 |
| 2005 |
|---|
| 8 | EE | Niklas Therning,
Lars Bengtsson:
Jalapeno: secentralized grid computing using peer-to-peer technology.
Conf. Computing Frontiers 2005: 59-65 |
| 7 | EE | Andreas Lindahl,
Lars Bengtsson:
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation.
DSD 2005: 42-47 |
| 2004 |
|---|
| 6 | EE | Minh Quang Do,
Per Larsson-Edefors,
Lars Bengtsson:
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.
PATMOS 2004: 869-878 |
| 2003 |
|---|
| 5 | | Minh Quang Do,
Lars Bengtsson,
Per Larsson-Edefors:
DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.
Applied Informatics 2003: 767-772 |
| 4 | EE | Anders Lindström,
Michael Nordseth,
Lars Bengtsson,
Amos Omondi:
Arithmetic Circuits Combining Residue and Signed-Digit Representations.
Asia-Pacific Computer Systems Architecture Conference 2003: 246-257 |
| 3 | | Lars Bengtsson:
A VLSI Array Architecture for Artificial Neural Networks.
Neural Networks and Computational Intelligence 2003: 50-57 |
| 2001 |
|---|
| 2 | EE | Stefan Lund,
Lars Bengtsson:
Synchronizing a High-Speed SIMD Processor Array.
DSD 2001: 376-381 |
| 1999 |
|---|
| 1 | | Lars Bengtsson:
Clock Speed Limitation and Timing in a Radar Signal Processing Architecture.
SIP 1999: 372-377 |
