| 2007 |
|---|
| 6 | EE | Minh Quang Do,
Per Larsson-Edefors,
Mindaugas Drazdziulis:
High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.
DSD 2007: 249-256 |
| 5 | EE | Minh Quang Do,
Mindaugas Drazdziulis,
Per Larsson-Edefors,
Lars Bengtsson:
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
ISQED 2007: 185-191 |
| 4 | EE | Mindaugas Drazdziulis,
Per Larsson-Edefors,
Lars J. Svensson:
Overdrive Power-Gating Techniques for Total Power Minimization.
ISVLSI 2007: 125-132 |
| 2006 |
|---|
| 3 | EE | Minh Quang Do,
Mindaugas Drazdziulis,
Per Larsson-Edefors,
Lars Bengtsson:
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.
ISQED 2006: 557-563 |
| 2005 |
|---|
| 2 | EE | Magnus Själander,
Mindaugas Drazdziulis,
Per Larsson-Edefors,
Henrik Eriksson:
A low-leakage twin-precision multiplier using reconfigurable power gating.
ISCAS (2) 2005: 1654-1657 |
| 2004 |
|---|
| 1 | | Mindaugas Drazdziulis,
Per Larsson-Edefors:
Evaluation of power cut-off techniques in the presence of gate leakage.
ISCAS (2) 2004: 745-748 |
