| 2009 |
|---|
| 6 | EE | Yann Oddos,
Katell Morin-Allory,
Dominique Borrione,
Marc Boule,
Zeljko Zilic:
MYGEN: automata-based on-line test generator for assertion-based verification.
ACM Great Lakes Symposium on VLSI 2009: 75-80 |
| 2008 |
|---|
| 5 | EE | Marc Boule,
Zeljko Zilic:
Automata-based assertion-checker synthesis of PSL properties.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 2007 |
|---|
| 4 | EE | Marc Boule,
Zeljko Zilic:
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation.
ASP-DAC 2007: 324-329 |
| 3 | EE | Marc Boule,
Jean-Samuel Chenard,
Zeljko Zilic:
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis.
ISQED 2007: 613-620 |
| 2006 |
|---|
| 2 | EE | Marc Boule,
Jean-Samuel Chenard,
Zeljko Zilic:
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.
ICCD 2006 |
| 2005 |
|---|
| 1 | EE | Marc Boule,
Zeljko Zilic:
Incorporating Ef.cient Assertion Checkers into Hardware Emulation.
ICCD 2005: 221-228 |
