| 2007 |
|---|
| 4 | EE | Rajsekhar Adapa,
Edward Flanigan,
Spyros Tragoudas,
Michael Laisne,
Hailong Cui,
Tsvetomir Petrov:
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
ISQED 2007: 717-722 |
| 3 | EE | Edward Flanigan,
Rajsekhar Adapa,
Hailong Cui,
Michael Laisne,
Spyros Tragoudas,
Tsvetomir Petrov:
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.
VLSI Design 2007: 805-812 |
| 2003 |
|---|
| 2 | EE | Hailong Cui,
Sharad C. Seth,
Shashank K. Mehta:
Modeling Fault Coverage of Random Test Patterns.
J. Electronic Testing 19(3): 271-284 (2003) |
| 2002 |
|---|
| 1 | EE | Hailong Cui,
Sharad C. Seth,
Shashank K. Mehta:
A Novel Method to Improve the Test Efficiency of VLSI Tests.
VLSI Design 2002: 499-504 |
