| 2008 |
|---|
| 9 | EE | Yongqiang Lu,
Qing Su,
Jamil Kawa:
An innovative Steiner tree based approach for polygon partitioning.
ASP-DAC 2008: 358-363 |
| 8 | EE | Qing Su,
Charles Chiang,
Jamil Kawa:
Hotspot Based Yield Prediction with Consideration of Correlations.
ISQED 2008: 338-343 |
| 2007 |
|---|
| 7 | | Maria Gkatziani,
Rohit Kapur,
Qing Su,
Ben Mathew,
Roberto Mattiuzzo,
Laura Tarantini,
Cy Hay,
Salvatore Talluto,
Thomas W. Williams:
Accurately Determining Bridging Defects from Layout.
DDECS 2007: 87-90 |
| 6 | EE | Subarna Sinha,
Qing Su,
Linni Wen,
Frank Lee,
Charles Chiang,
Yi-Kan Cheng,
Jin-Lien Lin,
Yu-Chyi Harn:
A New Flexible Algorithm for Random Yield Improvement.
ISQED 2007: 795-800 |
| 2006 |
|---|
| 5 | EE | Jianfeng Luo,
Subarna Sinha,
Qing Su,
Jamil Kawa,
Charles Chiang:
An IC manufacturing yield model considering intra-die variations.
DAC 2006: 749-754 |
| 4 | EE | Qing Su,
Jamil Kawa,
Charles Chiang,
Yehia Massoud:
Accurate modeling of substrate resistive coupling for floating substrates.
ACM Trans. Design Autom. Electr. Syst. 11(1): 44-51 (2006) |
| 2005 |
|---|
| 3 | | Jianfeng Luo,
Qing Su,
Charles Chiang,
Jamil Kawa:
A layout dependent full-chip copper electroplating topography model.
ICCAD 2005: 133-140 |
| 2 | EE | Xin Wang,
Charles Chiang,
Jamil Kawa,
Qing Su:
A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing.
ISQED 2005: 258-263 |
| 2003 |
|---|
| 1 | EE | Charles Chiang,
Qing Su,
Ching-Shoei Chiang:
Wirelength reduction by using diagonal wire.
ACM Great Lakes Symposium on VLSI 2003: 104-107 |
