| 2007 |
|---|
| 5 | EE | Minh Quang Do,
Per Larsson-Edefors,
Mindaugas Drazdziulis:
High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.
DSD 2007: 249-256 |
| 4 | EE | Minh Quang Do,
Mindaugas Drazdziulis,
Per Larsson-Edefors,
Lars Bengtsson:
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
ISQED 2007: 185-191 |
| 2006 |
|---|
| 3 | EE | Minh Quang Do,
Mindaugas Drazdziulis,
Per Larsson-Edefors,
Lars Bengtsson:
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.
ISQED 2006: 557-563 |
| 2004 |
|---|
| 2 | EE | Minh Quang Do,
Per Larsson-Edefors,
Lars Bengtsson:
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.
PATMOS 2004: 869-878 |
| 2003 |
|---|
| 1 | | Minh Quang Do,
Lars Bengtsson,
Per Larsson-Edefors:
DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.
Applied Informatics 2003: 767-772 |
