| |
| 2007 | ||
|---|---|---|
| 1 | EE | Eunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang: Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design. ISQED 2007: 573-579 |
| 1 | Kiwon Choi | [1] |
| 2 | Woojin Jin | [1] |
| 3 | Heeseok Lee | [1] |
| 4 | Jungtae Lee | [1] |
| 5 | Eunseok Song | [1] |