| |
| 2008 | ||
|---|---|---|
| 2 | EE | Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty: A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. VLSI Design 2008: 39-44 |
| 2007 | ||
| 1 | EE | Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty: A TMR Scheme for SEU Mitigation in Scan Flip-Flops. ISQED 2007: 905-910 |
| 1 | Tapan J. Chakraborty | [1] [2] |
| 2 | Roystein Oliveira | [1] [2] |