| 2008 |
|---|
| 3 | EE | Kumar Yelamarthi,
Chien-In Henry Chen:
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.
ISQED 2008: 143-147 |
| 2 | EE | Kumar Yelamarthi,
Chien-In Henry Chen:
Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.
JCP 3(2): 21-28 (2008) |
| 2007 |
|---|
| 1 | EE | Kumar Yelamarthi,
Chien-In Henry Chen:
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.
ISQED 2007: 426-431 |
