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Taraneh Taghavi

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2007
9EEShigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh: Block placement to ensure channel routability. ACM Great Lakes Symposium on VLSI 2007: 465-468
8EETaraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh: System Level Estimation of Interconnect Length in the Presence of IP Blocks. ISQED 2007: 438-443
7EETaraneh Taghavi, Majid Sarrafzadeh: Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks. ISVLSI 2007: 213-218
6EETaraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh: Tutorial on congestion prediction. SLIP 2007: 15-24
2006
5EETaraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh: Routing algorithms: architecture driven rerouting enhancement for FPGAs. ISCAS 2006
4EETaraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh: Dragon2006: blockage-aware congestion-controlling mixed-size placer. ISPD 2006: 209-211
2005
3EETaraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh: Routing algorithms: enhancing routability & enabling ECO (abstract only). FPGA 2005: 266
2EETaraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi: Dragon2005: large-scale mixed-size placement tool. ISPD 2005: 245-247
2004
1EETaraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh: Innovate or perish: FPGA physical design. ISPD 2004: 148-155

Coauthor Index

1Bo-Kyung Choi [2] [4]
2Foad Dabiri [6]
3Soheil Ghiasi [1] [3] [5]
4Zohreh Karimi [9]
5Ani Nahapetian [6] [8]
6Shigetoshi Nakatake [9]
7Salil Raje [1]
8Abhishek Ranjan [1]
9Majid Sarrafzadeh [1] [3] [4] [5] [6] [7] [8] [9]
10Maogang Wang [4]
11Xiaojian Yang [2] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)