| 2007 |
|---|
| 9 | EE | Shigetoshi Nakatake,
Zohreh Karimi,
Taraneh Taghavi,
Majid Sarrafzadeh:
Block placement to ensure channel routability.
ACM Great Lakes Symposium on VLSI 2007: 465-468 |
| 8 | EE | Taraneh Taghavi,
Ani Nahapetian,
Majid Sarrafzadeh:
System Level Estimation of Interconnect Length in the Presence of IP Blocks.
ISQED 2007: 438-443 |
| 7 | EE | Taraneh Taghavi,
Majid Sarrafzadeh:
Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks.
ISVLSI 2007: 213-218 |
| 6 | EE | Taraneh Taghavi,
Foad Dabiri,
Ani Nahapetian,
Majid Sarrafzadeh:
Tutorial on congestion prediction.
SLIP 2007: 15-24 |
| 2006 |
|---|
| 5 | EE | Taraneh Taghavi,
Soheil Ghiasi,
Majid Sarrafzadeh:
Routing algorithms: architecture driven rerouting enhancement for FPGAs.
ISCAS 2006 |
| 4 | EE | Taraneh Taghavi,
Xiaojian Yang,
Bo-Kyung Choi,
Maogang Wang,
Majid Sarrafzadeh:
Dragon2006: blockage-aware congestion-controlling mixed-size placer.
ISPD 2006: 209-211 |
| 2005 |
|---|
| 3 | EE | Taraneh Taghavi,
Soheil Ghiasi,
Majid Sarrafzadeh:
Routing algorithms: enhancing routability & enabling ECO (abstract only).
FPGA 2005: 266 |
| 2 | EE | Taraneh Taghavi,
Xiaojian Yang,
Bo-Kyung Choi:
Dragon2005: large-scale mixed-size placement tool.
ISPD 2005: 245-247 |
| 2004 |
|---|
| 1 | EE | Taraneh Taghavi,
Soheil Ghiasi,
Abhishek Ranjan,
Salil Raje,
Majid Sarrafzadeh:
Innovate or perish: FPGA physical design.
ISPD 2004: 148-155 |
