| 2008 |
|---|
| 6 | EE | Ashok Narasimhan,
Ramalingam Sridhar:
A low power and low area active clock deskewing technique for sub-90nm technologies.
SoCC 2008: 179-182 |
| 2007 |
|---|
| 5 | EE | Ashok Narasimhan,
Ramalingam Sridhar:
Impact of Variability on Clock Skew in H-tree Clock Networks.
ISQED 2007: 458-466 |
| 2006 |
|---|
| 4 | EE | Ashok Narasimhan,
Bhooma Srinivasaraghavan,
Ramalingam Sridhar:
A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.
VLSI Design 2006: 491-494 |
| 3 | EE | Prachee Sharma,
Asheq Khan,
Ashok Narasimhan,
Ramalingam Sridhar,
Satish K. Tripathi:
Energy Conservation in Sensor Networks through Selective Node Activation.
WOWMOM 2006: 115-124 |
| 2005 |
|---|
| 2 | EE | Ashok Narasimhan,
Shantanu Divekar,
Praveen Elakkumanan,
Ramalingam Sridhar:
A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs.
VLSI Design 2005: 130-133 |
| 1 | EE | Ashok Narasimhan,
Manish Kasotiya,
Ramalingam Sridhar:
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.
VLSI Design 2005: 634-639 |
