Andrew E. Caldwell

2004
18	EE	Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong: Effective iterative techniques for fingerprinting design IP. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 208-215 (2004)
2003
17	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hierarchical whitespace allocation in top-down placement. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1550-1556 (2003)
2002
16	EE	Andrew E. Caldwell, Igor L. Markov: Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms. IEEE Design & Test of Computers 19(3): 72-81 (2002)
2000
15	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Improved algorithms for hypergraph bipartitioning. ASP-DAC 2000: 661-666
14	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Can recursive bisection alone produce routable placements? DAC 2000: 477-482
13	EE	Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698
12	EE	Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng: Admissibility Proofs for the LCS* Algorithm. IBERAMIA-SBIA 2000: 236-244
11	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. ACM Journal of Experimental Algorithmics 5: 5 (2000)
10	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1304-1313 (2000)
9	EE	Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 267-272 (2000)
1999
8	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. ALENEX 1999: 177-193
7	EE	Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov: Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC 1999: 349-354
6	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hypergraph Partitioning with Fixed Vertices. DAC 1999: 355-359
5	EE	Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong: Effective Iterative Techniques for Fingerprinting Design IP. DAC 1999: 843-848
4	EE	Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Partitioning with terminals: a "new" problem and new benchmarks. ISPD 1999: 151-157
3	EE	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Optimal partitioners and end-case placers for standard-cell layout. ISPD 1999: 90-96
2	EE	Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky: On wirelength estimations for row-based placement. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1265-1278 (1999)
1998
1	EE	Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky: On wirelength estimations for row-based placement. ISPD 1998: 4-11

Coauthor Index

1	Charles J. Alpert	[4] [9]
2	Yu Cao	[13]
3	Hyun-Jin Choi	[5] [18]
4	Marcelo de Oliveira Johann (Marcelo O. Johann)	[12]
5	Andrew B. Kahng	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [17] [18]
6	Andrew A. Kennings	[7]
7	Farinaz Koushanfar	[13]
8	Hua Lu	[13]
9	Stefanus Mantik	[1] [2] [5] [18]
10	Igor L. Markov	[1] [2] [3] [4] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16] [17]
11	Michael Oliver	[13]
12	Miodrag Potkonjak	[5] [18]
13	Gang Qu	[5] [18]
14	Ricardo Augusto da Luz Reis (Ricardo A. L. Reis, Ricardo Reis)	[12]
15	Dirk Stroobandt	[13]
16	Dennis Sylvester	[13]
17	Jennifer L. Wong	[5] [18]
18	Alexander Zelikovsky	[1] [2]