H. C. Srinivasaiah

List of publications from the DBLP Bibliography Server - FAQ

2004

3 EE H. C. Srinivasaiah, Navakanta Bhat: Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. VLSI Design 2004: 285-290

2003

2 EE H. C. Srinivasaiah, Navakanta Bhat: Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 742-747 (2003)

2002

1 EE H. C. Srinivasaiah, Navakanta Bhat: Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. VLSI Design 2002: 225-

2004
3	EE	H. C. Srinivasaiah, Navakanta Bhat: Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. VLSI Design 2004: 285-290
2003
2	EE	H. C. Srinivasaiah, Navakanta Bhat: Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 742-747 (2003)
2002
1	EE	H. C. Srinivasaiah, Navakanta Bhat: Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. VLSI Design 2002: 225-

Coauthor Index