| 2006 |
|---|
| 37 | EE | Peter M. Maurer:
Using conjugate symmetries to enhance gate-level simulations.
DATE 2006: 638-643 |
| 2005 |
|---|
| 36 | | William B. Poucher,
Peter M. Maurer:
How to Make Program Assessment Work for You.
FECS 2005: 83-87 |
| 35 | EE | Peter M. Maurer:
Converting command-line applications into binary components.
Softw., Pract. Exper. 35(8): 787-797 (2005) |
| 2004 |
|---|
| 34 | EE | Peter M. Maurer:
Metamorphic Programming: Unconventional High Performance.
IEEE Computer 37(3): 30-38 (2004) |
| 2003 |
|---|
| 33 | EE | Sandeep K. Kondapuram,
Peter M. Maurer:
Random Characterization of Design Automation Algorithms.
ISVLSI 2003: 264-265 |
| 32 | EE | Peter M. Maurer:
Efficient event-driven simulation by exploiting the output observability of gate clusters.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1471-1486 (2003) |
| 2001 |
|---|
| 31 | EE | Allen S. Parrish,
Joe Hollingsworth,
Peter M. Maurer,
Benjamin Shults,
Bruce W. Weide:
Identifying an appropriate view of software components for undergraduate education.
SIGCSE 2001: 394-395 |
| 2000 |
|---|
| 30 | EE | Peter M. Maurer:
Logic Simulation Using Networks of State Machines.
DATE 2000: 674-678 |
| 29 | | Peter M. Maurer:
Event Driven Simulation Without Loops or Conditionals.
ICCAD 2000: 23-26 |
| 28 | EE | Peter M. Maurer,
William J. Schilp:
State-Machine Based Logic Simulation Using Three Logic Values.
VLSI Design 2000: 430-435 |
| 27 | EE | Peter M. Maurer:
Components: What If They Gave a Revolution and Nobody Came?
IEEE Computer 33(6): 28-34 (2000) |
| 1999 |
|---|
| 26 | EE | Peter M. Maurer,
William J. Schilp:
Software Bit-Slicing: A Technique for Improving Simulation Performance.
DATE 1999: 786-787 |
| 25 | EE | Peter M. Maurer:
Efficient Simulation for Hierarchical and Partitioned Circuits.
VLSI Design 1999: 236-241 |
| 1997 |
|---|
| 24 | EE | Peter M. Maurer:
The inversion algorithm for digital simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 762-769 (1997) |
| 1996 |
|---|
| 23 | EE | William J. Schilp,
Peter M. Maurer:
Unit delay simulation with the inversion algorithm.
ICCAD 1996: 412-417 |
| 22 | EE | Peter M. Maurer:
Is Compiled Simulation Really Faster than Interpreted Simulation?
VLSI Design 1996: 303-306 |
| 21 | EE | Yun Sik Lee,
Peter M. Maurer:
Bit-parallel multidelay simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1547-1554 (1996) |
| 1994 |
|---|
| 20 | EE | Peter M. Maurer:
The Inversion Algorithm for digital simulation.
ICCAD 1994: 258-261 |
| 19 | EE | Peter M. Maurer,
Yun Sik Lee:
Gateways: a technique for adding event-driven behavior to compiled simulations.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 338-352 (1994) |
| 1993 |
|---|
| 18 | EE | Yun Sik Lee,
Peter M. Maurer:
Parallel multi-delay simulation.
ICCAD 1993: 759-762 |
| 17 | EE | Peter M. Maurer:
The shadow algorithm: a scheduling technique for both compiled and interpreted simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1411-1413 (1993) |
| 1992 |
|---|
| 16 | EE | Yun Sik Lee,
Peter M. Maurer:
Two New Techniques for Compiled Multi-Delay Logic Simulation.
DAC 1992: 420-423 |
| 15 | EE | Peter M. Maurer:
Two new techniques for unit-delay compiled simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1120-1130 (1992) |
| 14 | | Peter M. Maurer:
The Design and Implementation of a Grammar-based Data Generator.
Softw., Pract. Exper. 22(3): 223-244 (1992) |
| 1991 |
|---|
| 13 | EE | Peter M. Maurer:
Scheduling blocks of hierarchical compiled simulation of combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(2): 184-192 (1991) |
| 1990 |
|---|
| 12 | EE | Peter M. Maurer:
The FHDL macro processor.
ACM Southeast Regional Conference 1990: 10-17 |
| 11 | EE | Peter M. Maurer,
Craig D. Morency:
The FHDL ROM tools.
ACM Southeast Regional Conference 1990: 18-24 |
| 10 | EE | Peter M. Maurer,
Craig D. Morency:
The FHDL PLA tools.
ACM Southeast Regional Conference 1990: 3-9 |
| 9 | EE | Peter M. Maurer,
Zhicheng Wang:
Techniques for Unit-Delay Compiled Simulation.
DAC 1990: 480-484 |
| 8 | EE | Zhicheng Wang,
Peter M. Maurer:
LECSIM: A Levelized Event Driven Compiled Logic Simulation.
DAC 1990: 491-496 |
| 7 | | Peter M. Maurer:
Optimization of the Parallel Technique for Compiled Unit-Delay Simulation.
ICCAD 1990: 70-73 |
| 6 | EE | Peter M. Maurer:
Dynamic Functional Testing for VLSI Circuits.
IEEE Design & Test of Computers 7(6): 42-49 (1990) |
| 5 | | Peter M. Maurer:
Generating Test Data with Enhanced Context-Free Grammars.
IEEE Software 7(4): 50-55 (1990) |
| 1989 |
|---|
| 4 | EE | Zhicheng Wang,
Peter M. Maurer:
Scheduling High-Level Blocks for Functional Simulation.
DAC 1989: 87-90 |
| 1988 |
|---|
| 3 | | Peter M. Maurer:
Mapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor.
ICPP (1) 1988: 235-239 |
| 2 | EE | Peter M. Maurer,
Alexander D. Schapira:
A logic-to-logic comparator for VLSI layout verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 897-907 (1988) |
| 1983 |
|---|
| 1 | | Peter M. Maurer,
Arthur E. Oldehoeft:
The Use of Combinators in Translating A Purely Functional Language to Low-Level Data-Flow Graphs.
Comput. Lang. 8(1): 27-45 (1983) |
