Jih-Jeen Chen

List of publications from the DBLP Bibliography Server - FAQ

2003

5 EE Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee: Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003)

2002

4 EE Kuen-Jong Lee, Jih-Jeen Chen: Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Asian Test Symposium 2002: 338-

2000

3 EE Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen: Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458

1999

2 EE Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Broadcasting test patterns to multiple circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1793-1802 (1999)

1998

1 EE Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Using a single input to support multiple scan chains. ICCAD 1998: 74-78

2003
5	EE	Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee: Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003)
2002
4	EE	Kuen-Jong Lee, Jih-Jeen Chen: Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Asian Test Symposium 2002: 338-
2000
3	EE	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen: Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458
1999
2	EE	Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Broadcasting test patterns to multiple circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1793-1802 (1999)
1998
1	EE	Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Using a single input to support multiple scan chains. ICCAD 1998: 74-78

Coauthor Index