| 2003 |
|---|
| 10 | EE | Haitian Hu,
David Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
ISCAS (4) 2003: 668-671 |
| 9 | EE | Haitian Hu,
David T. Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003) |
| 8 | EE | Haihua Su,
Kaushik Gala,
Sachin S. Sapatnekar:
Analysis and optimization of structured power/ground networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1533-1544 (2003) |
| 2002 |
|---|
| 7 | EE | Haitian Hu,
David Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance.
ICCAD 2002: 221-227 |
| 6 | EE | Min Zhao,
Kaushik Gala,
Vladimir Zolotov,
Yuhong Fu,
Rajendran Panda,
R. Ramkumar,
Bhuwan K. Agrawal:
Worst case clock skew under power supply variations.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 22-28 |
| 5 | EE | Kaushik Gala,
David Blaauw,
Vladimir Zolotov,
P. M. Vaidya,
A. Joshi:
Inductance model and analysis methodology for high-speed on-chip interconnect.
IEEE Trans. VLSI Syst. 10(6): 730-745 (2002) |
| 2001 |
|---|
| 4 | EE | Kaushik Gala,
David Blaauw,
Junfeng Wang,
Vladimir Zolotov,
Min Zhao:
Inductance 101: Analysis and Design Issues.
DAC 2001: 329-334 |
| 2000 |
|---|
| 3 | EE | David Blaauw,
Kaushik Gala,
Vladimir Zolotov,
Rajendran Panda,
Junfeng Wang:
On-chip inductance modeling.
ACM Great Lakes Symposium on VLSI 2000: 75-80 |
| 2 | EE | Kaushik Gala,
Vladimir Zolotov,
Rajendran Panda,
Brian Young,
Junfeng Wang,
David Blaauw:
On-chip inductance modeling and analysis.
DAC 2000: 63-68 |
| 1 | | Haihua Su,
Kaushik Gala,
Sachin S. Sapatnekar:
Fast Analysis and Optimization of Power/Ground Networks.
ICCAD 2000: 477-480 |
