| 2003 |
|---|
| 5 | EE | Haitian Hu,
David Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
ISCAS (4) 2003: 668-671 |
| 4 | EE | Haitian Hu,
David T. Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003) |
| 2002 |
|---|
| 3 | EE | Haitian Hu,
David Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance.
ICCAD 2002: 221-227 |
| 2 | EE | Haitian Hu,
Sachin S. Sapatnekar:
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques.
ICCD 2002: 434- |
| 1 | EE | Haitian Hu,
Sachin S. Sapatnekar:
Efficient inductance extraction using circuit-aware techniques.
IEEE Trans. VLSI Syst. 10(6): 746-761 (2002) |
