| 2004 |
| 11 | EE | Chih-Wei Jim Chang,
Ming-Fu Hsiao,
Bo Hu,
Kai Wang,
Malgorzata Marek-Sadowska,
Chung-Kuan Cheng,
Sao-Jie Chen:
Fast postplacement optimization using functional symmetries.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 102-118 (2004) |
| 2003 |
| 10 | EE | Chih-Wei Jim Chang,
Ming-Fu Hsiao,
Malgorzata Marek-Sadowska:
A new reasoning scheme for efficient redundancy addition and removal.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 945-951 (2003) |
| 2002 |
| 9 | EE | Chih-Wei Jim Chang,
Malgorzata Marek-Sadowska:
ATPG-based logic synthesis: an overview.
ICCAD 2002: 786-789 |
| 2001 |
| 8 | EE | Chih-Wei Jim Chang,
Malgorzata Marek-Sadowska:
Who are the alternative wires in your neighborhood? (alternative wires identification without search).
ACM Great Lakes Symposium on VLSI 2001: 103-108 |
| 7 | EE | Chih-Wei Jim Chang,
Kai Wang,
Malgorzata Marek-Sadowska:
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques.
DAC 2001: 97-102 |
| 6 | EE | Chih-Wei Jim Chang,
Bo Hu,
Malgorzata Marek-Sadowska:
In-place delay constrained power optimization using functional symmetries.
DATE 2001: 377-382 |
| 5 | EE | Chih-Wei Jim Chang,
Malgorzata Marek-Sadowska:
Single-Pass Redundancy Addition and Removal.
ICCAD 2001: 606-609 |
| 2000 |
| 4 | EE | Chih-Wei Jim Chang,
Chung-Kuan Cheng,
Peter Suaris,
Malgorzata Marek-Sadowska:
Fast post-placement rewiring using easily detectable functional symmetries.
DAC 2000: 286-289 |
| 1989 |
| 3 | | Sun-Yuan Kung,
Shiann-Ning Jean,
Chih-Wei Jim Chang:
Fault-Tolerant Array Processors Using Single-Track Switches.
IEEE Trans. Computers 38(4): 501-514 (1989) |
| 1988 |
| 2 | | Shiann-Ning Jean,
Chih-Wei Jim Chang,
Sun-Yuan Kung:
Graceful Degradation Schemes for Static/Dynamic Wavefront Arrays.
ICPP (1) 1988: 249-255 |
| 1986 |
| 1 | | Sun-Yuan Kung,
Chih-Wei Jim Chang,
Chein-Wei Jen:
Real-Time Configuration for Fault-Tolerant VLSI Array Processors.
IEEE Real-Time Systems Symposium 1986: 46-54 |