2008 |
14 | EE | Per Bjesse:
A Practical Approach to Word Level Model Checking of Industrial Netlists.
CAV 2008: 446-458 |
2007 |
13 | EE | In-Ho Moon,
Per Bjesse,
Carl Pixley:
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.
DATE 2007: 1170-1175 |
2005 |
12 | | Per Bjesse,
James H. Kukula:
Automatic generalized phase abstraction for formal verification.
ICCAD 2005: 1076-1082 |
2004 |
11 | EE | Per Bjesse,
James H. Kukula:
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs.
DATE 2004: 156-161 |
10 | EE | Per Bjesse,
Arne Borälv:
DAG-aware circuit compression for formal verification.
ICCAD 2004: 42-49 |
2003 |
9 | EE | Per Bjesse,
James H. Kukula,
Robert F. Damiano,
Ted Stanion,
Yunshan Zhu:
Guiding SAT Diagnosis with Tree Decompositions.
SAT 2003: 315-329 |
8 | EE | Gunnar Andersson,
Per Bjesse,
Byron Cook,
Ziyad Hanna:
Design automation with mixtures of proof strategies for propositional logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1042-1048 (2003) |
2002 |
7 | EE | Gunnar Andersson,
Per Bjesse,
Byron Cook,
Ziyad Hanna:
A proof engine approach to solving combinational design automation problems.
DAC 2002: 725-730 |
6 | EE | Per Bjesse:
Industrial Model Checking Based on Satisfiability Solvers.
SPIN 2002: 240 |
2001 |
5 | EE | Per Bjesse,
Tim Leonard,
Abdel Mokkedem:
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers.
CAV 2001: 454-464 |
2000 |
4 | EE | Per Bjesse,
Koen Claessen:
SAT-Based Verification without State Space Traversal.
FMCAD 2000: 372-389 |
3 | EE | Parosh Aziz Abdulla,
Per Bjesse,
Niklas Eén:
Symbolic Reachability Analysis Based on SAT-Solvers.
TACAS 2000: 411-425 |
1999 |
2 | EE | Per Bjesse:
Automatic Verification of Combinatorial and Pipelined FFT.
CAV 1999: 380-393 |
1998 |
1 | EE | Per Bjesse,
Koen Claessen,
Mary Sheeran,
Satnam Singh:
Lava: Hardware Design in Haskell.
ICFP 1998: 174-184 |