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Asim J. Al-Khalili

A. J. Al-Khalili

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2009
32EEHouman Zarrabi, Asim J. Al-Khalili, Yvon Savaria: An interconnect-aware delay model for dynamic voltage scaling in NM technologies. ACM Great Lakes Symposium on VLSI 2009: 45-50
2006
31EEAsim J. Al-Khalili: A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers. ICN/ICONS/MCL 2006: 183
30EEHouman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria: Zero skew differential clock distribution network. ISCAS 2006
2005
29EEShaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy: An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. IWSOC 2005: 396-399
28EEHaydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili: Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1637-1643 (2005)
27EEAdnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili: Delay analysis of CMOS gates using modified logical effort model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 937-947 (2005)
2004
26 Shaoqiang Bi, Wei Wang, Asim J. Al-Khalili: Modulo deflation in (2n+1, 2n, 2n-1) converters. ISCAS (2) 2004: 429-432
2003
25EEAsim J. Al-Khalili, Aiping Hu: Design of a 32-bit squarer - exploiting addition redundancy. ISCAS (5) 2003: 325-328
24EEAdnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili: Technology-portable analytical model for DSM CMOS inverter transition-time estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1177-1187 (2003)
23EECheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch: Low-Power Constant-Coefficient Multiplier Generator. VLSI Signal Processing 35(2): 187-194 (2003)
2002
22EEHaydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili: Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 119-125
2001
21EER. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah: A Low Power Approach to Floating Point Adder Design for DSP Applications. VLSI Signal Processing 27(3): 195-213 (2001)
1999
20EER. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Power implications of precision limited arithmetic in floating point FIR filters. ISCAS (1) 1999: 165-168
19EEAdnan Kabbani, A. J. Al-Khalili: Dynamic CMOS noise immunity estimation in submicron regime. ISCAS (1) 1999: 529-532
18EEAdnan Kabbani, A. J. Al-Khalili: Estimation of ground bounce effects on CMOS circuits. ISCAS (1) 1999: 533-536
17 R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: An IEEE Compliant Floating Point MAF. VLSI 1999: 149-160
16EEJacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili: Lossy Compression of Images Using Logic Minimization. VLSI Design 1999: 538-543
1998
15EER. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili: A Low Power Floating Point Accumulator. VLSI Design 1998: 330-
1997
14 R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: A Low Power Approach to Floating Point Adder Design. ICCD 1997: 178-185
13EER. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. ISLPED 1997: 235-238
1996
12EER. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Energy delay analysis of partial product reduction methods for parallel multiplier implementation. ISLPED 1996: 201-204
1995
11EEMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Area efficient computing structures for concurrent error detection in systolic arrays. VLSI Signal Processing 10(3): 237-260 (1995)
10EEMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili: Design techniques for fault-tolerant systolic arrays. VLSI Signal Processing 11(1-2): 151-168 (1995)
1992
9EEF. Rouatbi, Baher Haroun, Asim J. Al-Khalili: Power estimation tool for sub-micron CMOS VLSI circuits. ICCAD 1992: 204-209
8 Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Design Methodology for Fault-Tolerant Systolic Array Architectures. ICPP (2) 1992: 267-274
1991
7 Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures. ICPP (1) 1991: 484-491
6 Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: On the Design of Optimal Fault-Tolerant Systolic Array Architecures. IPPS 1991: 352-357
1990
5EEMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Design of optimal systolic arrays: a systematic approach. SPDP 1990: 166-173
4EEAsim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili: A module generator for optimized CMOS buffers. IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1028-1046 (1990)
1989
3EEAsim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili: A Module Generator for Optimized CMOS Buffers. DAC 1989: 245-250
1984
2 Asim J. Al-Khalili: An Algorithm for an Intelligent Arabic Computer Terminal. International Journal of Man-Machine Studies 20(4): 331-341 (1984)
1973
1 C. J. Macleod, Asim J. Al-Khalili: An On-Line Optimization Procedure for an Urban Traffic System. Optimization Techniques 1973: 31-41

Coauthor Index

1Dhamin Al-Khalili [3] [4] [10] [12] [13] [14] [15] [17] [20] [21] [22] [24] [27] [28]
2Jacob Augustine [16]
3Shaoqiang Bi [26] [29]
4Michael Ogbonna Esonu [5] [6] [7] [8] [10] [11]
5Warren J. Gross [29]
6Salim Hariri [5] [6] [7] [8] [10] [11]
7Baher Haroun [9]
8Aiping Hu [25]
9Adnan Kabbani [18] [19] [24] [27]
10William E. Lynch [16] [23]
11C. J. Macleod [1]
12Mohamed Nekili [22] [28]
13Cheng-Yu Pai [23]
14R. V. K. Pillai [12] [13] [14] [15] [17] [20] [21]
15F. Rouatbi [9]
16Haydar Saaied [22] [28] [30]
17Yvon Savaria [30] [32]
18S. Y. A. Shah [21]
19M. N. S. Swamy [29]
20Yuke Wang [16]
21Wei Wang [26] [29]
22Houman Zarrabi [30] [32]
23Yong Zhu [3] [4]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)