| 2003 |
|---|
| 9 | EE | Junwei Hou,
Abhijit Chatterjee:
Concurrent transient fault simulation for analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1385-1398 (2003) |
| 2000 |
|---|
| 8 | EE | Junwei Hou,
Abhijit Chatterjee:
Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping.
ICCD 2000: 35-41 |
| 1999 |
|---|
| 7 | EE | Junwei Hou,
William H. Kao,
Abhijit Chatterjee:
A novel concurrent fault simulation method for mixed-signal circuits.
ISCAS (2) 1999: 448-451 |
| 6 | EE | Pramodchandran N. Variyam,
Junwei Hou,
Abhijit Chatterjee:
Test Generation for Analog Circuits Using Partial Numerical Simulation.
VLSI Design 1999: 597-602 |
| 5 | EE | Pramodchandran N. Variyam,
Junwei Hou,
Abhijit Chatterjee:
Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation.
VTS 1999: 214-219 |
| 4 | EE | Heebyung Yoon,
Junwei Hou,
Swapan K. Bhattacharya,
Abhijit Chatterjee,
Madhavan Swaminathan:
Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives.
VLSI Signal Processing 21(3): 265-276 (1999) |
| 1998 |
|---|
| 3 | EE | Junwei Hou,
Abhijit Chatterjee:
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits.
ICCAD 1998: 384-391 |
| 1997 |
|---|
| 2 | | Ramakrishna Voorakaranam,
Sudip Chakrabarti,
Junwei Hou,
Alfred V. Gomes,
Sasikumar Cherubal,
Abhijit Chatterjee,
William H. Kao:
Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis.
ITC 1997: 903-912 |
| 1996 |
|---|
| 1 | EE | Junwei Hou,
Wayne Wolf:
Process Partitioning for Distributed Embedded Systems.
CODES 1996: 70-76 |
