Noureddine Chabini

2007
14	EE	Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP 2007: 18-23
13	EE	Noureddine Chabini, Wayne Wolf: Register binding guided by the size of variables. ICCD 2007: 587-594
12	EE	Noureddine Chabini, Wayne Wolf: Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints. IESS 2007: 255-268
11	EE	Noureddine Chabini: A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. PATMOS 2007: 64-74
2005
10	EE	Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria: Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. ACM Trans. Design Autom. Electr. Syst. 10(2): 187-204 (2005)
9	EE	Noureddine Chabini, Wayne Wolf: Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints. IEEE Trans. VLSI Syst. 13(10): 1113-1126 (2005)
2004
8	EE	Noureddine Chabini, Wayne Wolf: An approach for reducing dynamic power consumption in synchronous sequential digital designs. ASP-DAC 2004: 198-204
7	EE	Noureddine Chabini, Wayne Wolf: An approach for integrating basic retiming and software pipelining. EMSOFT 2004: 287-296
6	EE	Noureddine Chabini, Wayne Wolf: Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. IEEE Trans. VLSI Syst. 12(6): 573-589 (2004)
2003
5	EE	Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria: Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. ACM Great Lakes Symposium on VLSI 2003: 221-224
4	EE	Noureddine Chabini, Wayne Wolf: Minimizing Variables' Lifetime in Loop-Intensive Applications. EMSOFT 2003: 100-116
3	EE	Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria: Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 346-351 (2003)
2001
2		Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria: Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. ICCD 2001: 546-552
1		Noureddine Chabini, Yvon Savaria: Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. ISSS 2001: 209-214

Coauthor Index

1	El Mostapha Aboulhamid	[2] [3] [5] [10]
2	Dhamin Al-Khalili	[14]
3	Ismaïl Chabini	[3] [5] [10]
4	Shuli Gao	[14]
5	J. M. Pierre Langlois	[14]
6	Yvon Savaria	[1] [2] [3] [5] [10]
7	Wayne Wolf	[4] [6] [7] [8] [9] [12] [13]

Colors in the list of coauthors