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Pradip A. Thaker

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2003
4EEPradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1104-1113 (2003)
2000
3 Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. ITC 2000: 940-949
1999
2EEPradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin: Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. VLSI Design 1999: 256-259
1EEPradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. VTS 1999: 182-188

Coauthor Index

1Vishwani D. Agrawal [1] [3] [4]
2Minesh B. Amin [2]
3Mona E. Zaghloul [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)