![]() | ![]() |
2003 | ||
---|---|---|
2 | EE | Bart De Smedt, Georges G. E. Gielen: HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits. DATE 2003: 10256-10263 |
1 | EE | Bart De Smedt, Georges G. E. Gielen: WATSON: design space boundary exploration and model generation for analog and RFIC design. IEEE Trans. on CAD of Integrated Circuits and Systems 22(2): 213-224 (2003) |
1 | Georges G. E. Gielen | [1] [2] |