| 2007 |
|---|
| 11 | EE | Debatosh Debnath,
Tsutomu Sasao:
A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks.
IEICE Transactions 90-A(5): 932-940 (2007) |
| 2006 |
|---|
| 10 | EE | Debatosh Debnath,
Tsutomu Sasao:
Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries.
IEICE Transactions 89-A(12): 3443-3450 (2006) |
| 2005 |
|---|
| 9 | EE | Debatosh Debnath,
Tsutomu Sasao:
Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs.
IEICE Transactions 88-A(12): 3332-3341 (2005) |
| 8 | EE | Debatosh Debnath,
Tsutomu Sasao:
Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders.
IEICE Transactions 88-D(7): 1492-1500 (2005) |
| 2004 |
|---|
| 7 | EE | Debatosh Debnath,
Tsutomu Sasao:
Efficient computation of canonical form for Boolean matching in large libraries.
ASP-DAC 2004: 591-596 |
| 2003 |
|---|
| 6 | EE | Debatosh Debnath,
Zvonko G. Vranesic:
A fast algorithm for OR-AND-OR synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1166-1176 (2003) |
| 2000 |
|---|
| 5 | EE | Debatosh Debnath,
Tsutomu Sasao:
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions.
ASP-DAC 2000: 247-252 |
| 1999 |
|---|
| 4 | EE | Debatosh Debnath,
Tsutomu Sasao:
Fast Boolean Matching Under Permutation Using Representative.
ASP-DAC 1999: 359-362 |
| 3 | EE | Debatosh Debnath,
Tsutomu Sasao:
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates.
ISMVL 1999: 99-104 |
| 1998 |
|---|
| 2 | | Debatosh Debnath,
Tsutomu Sasao:
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks.
ASP-DAC 1998: 69-74 |
| 1995 |
|---|
| 1 | EE | Debatosh Debnath,
Tsutomu Sasao:
GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions.
ASP-DAC 1995 |
