| 2003 |
|---|
| 9 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
SoC design integration by using automatic interconnection rectification.
ISCAS (4) 2003: 744-747 |
| 8 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 104-114 (2003) |
| 2002 |
|---|
| 7 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1225-1232 (2002) |
| 6 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 466-479 (2002) |
| 2001 |
|---|
| 5 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Asian Test Symposium 2001: 431-436 |
| 4 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An AVPG for SOC design verification with port order fault model.
ISCAS (5) 2001: 259-262 |
| 3 | EE | Chih-Yuan Chen,
Shing-Wu Tung:
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality.
ISQED 2001: 405-408 |
| 1998 |
|---|
| 2 | EE | Shing-Wu Tung,
Jing-Yang Jou:
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.
Asian Test Symposium 1998: 402-407 |
| 1 | EE | Shing-Wu Tung,
Jing-Yang Jou:
A Logical Fault Model for Library Coherence Checking.
J. Inf. Sci. Eng. 14(3): 567-586 (1998) |
