2005 | ||
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22 | EE | Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu: Charge-Based Core and the Model Architecture of BSIM5. ISQED 2005: 96-101 |
21 | EE | Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu: Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. IEEE Trans. VLSI Syst. 13(1): 158-162 (2005) |
2004 | ||
20 | EE | Jin He, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu: A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach. ISQED 2004: 45-50 |
2003 | ||
19 | EE | Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. VLSI Syst. 11(1): 3-14 (2003) |
18 | EE | Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu: Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003) |
17 | EE | Mansun Chan, Xuemei Xi, Jin He, Kanyu M. Cao, Mohan V. Dunga, Ali M. Niknejad, Ping K. Ko, Chenming Hu: Practical compact modeling approaches and options for sub-0.1 mum CMOS technologies. Microelectronics Reliability 43(3): 399-404 (2003) |
2002 | ||
16 | EE | Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu: Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. ISQED 2002: 487-491 |
15 | EE | Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design 2002: 77- |
14 | EE | Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu: Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. VLSI Syst. 10(6): 799-805 (2002) |
13 | EE | Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002) |
2001 | ||
12 | EE | Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie: Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. ISQED 2001: 185-190 |
2000 | ||
11 | Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester: Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61 | |
10 | Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67 | |
1999 | ||
9 | EE | Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu: On Thermal Effects in Deep Sub-Micron VLSI Interconnects. DAC 1999: 885-891 |
1998 | ||
8 | EE | Michael Orshansky, James C. Chen, Chenming Hu: A Statistical Performance Simulation Methodology for VLSI Circuits. DAC 1998: 402-407 |
7 | EE | Yuhua Cheng, Kai Chen, Kiyotaka Imai, Chenming Hu: A unified MOSFET channel charge model for device modeling in circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 641-644 (1998) |
1997 | ||
6 | EE | Kai Chen, Chenming Hu: Device and technology optimizations for low power design in deep sub-micron regime. ISLPED 1997: 312-316 |
1996 | ||
5 | EE | Kai Chen, Yuhua Cheng, Chenming Hu: Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. ISLPED 1996: 197-200 |
1993 | ||
4 | EE | Robert H. Tu, Elyse Rosenbaum, Wilson Y. Chan, Chester C. Li, Eric Minami, Khandker Quader, Ping K. Ko, Chenming Hu: Berkeley reliability tools-BERT. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1524-1534 (1993) |
1992 | ||
3 | EE | Hong June Park, Ping Keung Ko, Chenming Hu: A non-quasi-static MOSFET model for SPICE-AC analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1247-1257 (1992) |
1991 | ||
2 | EE | Hong June Park, Ping Keung Ko, Chenming Hu: A charge sheet capacitance model of short channel MOSFETs for SPICE. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 376-389 (1991) |
1 | EE | Hong June Park, Ping Keung Ko, Chenming Hu: A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 629-642 (1991) |