| 2006 |
|---|
| 12 | EE | Junhyung Um,
Woo-Cheol Kwon,
Sungpack Hong,
Young-Taek Kim,
Kyu-Myung Choi,
Jeong-Taek Kong,
Soo-Kwan Eo,
Taewhan Kim:
A systematic IP and bus subsystem modeling for platform-based system design.
DATE 2006: 560-564 |
| 11 | EE | Junhyung Um,
Taewhan Kim:
Resource Sharing Combined with Layout Effects in High-Level Synthesis.
VLSI Signal Processing 44(3): 231-243 (2006) |
| 2003 |
|---|
| 10 | EE | Junhyung Um,
Taewhan Kim:
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design.
ICCAD 2003: 197-200 |
| 9 | EE | Junhyung Um,
Sangwoo Lee,
Youngsoo Park,
Sungik Jun,
Thewhan KimU:
An efficient inverse multiplier/divider architecture for cryptography systems.
ISCAS (5) 2003: 149-152 |
| 8 | EE | Junhyung Um,
Taewhan Kim:
Synthesis of arithmetic circuits considering layout effects.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1487-1503 (2003) |
| 2002 |
|---|
| 7 | EE | Junhyung Um,
Taewhan Kim:
Layout-aware synthesis of arithmetic circuits.
DAC 2002: 207-212 |
| 6 | EE | Junhyung Um,
Jae-hoon Kim,
Taewhan Kim:
Layout-driven resource sharing in high-level synthesis.
ICCAD 2002: 614-618 |
| 2001 |
|---|
| 5 | EE | Junhyung Um,
Taewhan Kim:
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.
IEEE Trans. Computers 50(3): 215-233 (2001) |
| 2000 |
|---|
| 4 | EE | Taewhan Kim,
Junhyung Um:
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper).
ASP-DAC 2000: 313-316 |
| 3 | EE | Junhyung Um,
Taewhan Kim,
C. L. Liu:
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.
DAC 2000: 98-103 |
| 2 | EE | Taewhan Kim,
Junhyung Um:
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 615-624 (2000) |
| 1999 |
|---|
| 1 | EE | Junhyung Um,
Taewhan Kim,
C. L. Liu:
Optimal allocation of carry-save-adders in arithmetic optimization.
ICCAD 1999: 410-413 |
