| 2005 |
|---|
| 9 | EE | Yoon Huh,
Peter Bendix,
Kyungjin Min,
Jau-Wen Chen,
Ravindra Narayan,
Larry D. Johnson,
Steven H. Voldman:
ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited.
IWSOC 2005: 47-53 |
| 2004 |
|---|
| 8 | EE | Payman Zarkesh-Ha,
Ken Doniger,
William Loh,
Peter Bendix:
Prediction of interconnect adjacency distribution: derivation, validation, and applications.
SLIP 2004: 99-106 |
| 2003 |
|---|
| 7 | EE | Yannick L. Le Coz,
Dhivya Krishna,
Dusan M. Petranovic,
William M. Loh,
Peter Bendix:
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines.
ICCAD 2003: 665-671 |
| 6 | EE | Jaesik Lee,
Ki-Wook Kim,
Yoonjong Huh,
Peter Bendix,
Sung-Mo Kang:
Chip-level charged-device modeling and simulation in CMOS integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 67-81 (2003) |
| 2001 |
|---|
| 5 | | Jaesik Lee,
Yoonjong Huh,
Peter Bendix,
Sung-Mo Kang:
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems.
ICCD 2001: 406-414 |
| 4 | EE | Jaesik Lee,
Yoonjong Huh,
Peter Bendix,
Sung-Mo Kang:
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology.
ISCAS (4) 2001: 746-749 |
| 3 | EE | Q. Li,
Yoonjong Huh,
Jau-Wen Chen,
Peter Bendix,
Sung-Mo Kang:
ESD design rule checker.
ISCAS (5) 2001: 499-502 |
| 2 | EE | Q. Li,
Yoonjong Huh,
Jau-Wen Chen,
Peter Bendix,
Sung-Mo Kang:
Full chip ESD design rule checking.
ISCAS (5) 2001: 503-506 |
| 1 | EE | Peter Bendix:
Spice Model Quality: Process Development Viewpoint.
ISQED 2001: 477-481 |
