Chia-Kai Yang

List of publications from the DBLP Bibliography Server - FAQ

2003

1 EE Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee: Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003)

2003
1	EE	Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee: Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003)

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