Eric G. Mercer
List of publications from the
2009 |
19 | EE | Neha Rungta,
Eric G. Mercer:
Guided model checking for programs with polymorphism.
PEPM 2009: 21-30 |
2008 |
18 | EE | Neha Rungta,
Eric G. Mercer:
A Meta Heuristic for Effectively Detecting Concurrency Errors.
Haifa Verification Conference 2008: 23-37 |
17 | EE | Daniel D. Walker,
Eric G. Mercer,
Kent E. Seamons:
Or Best Offer: A Privacy Policy Negotiation Protocol.
POLICY 2008: 173-180 |
16 | EE | Rahul Kumar,
Eric G. Mercer:
Improving Live Sequence Chart to Automata Transformation for Verification.
ECEASST 10: (2008) |
2007 |
15 | EE | Neha Rungta,
Hyrum Carroll,
Eric G. Mercer,
Randall J. Roper,
Mark J. Clement,
Quinn Snell:
Analyzing Gene Relationships for Down Syndrome with Labeled Transition Graphs.
FMCAD 2007: 216-219 |
14 | EE | Neha Rungta,
Eric G. Mercer:
Hardness for Explicit State Software Model Checking Benchmarks.
SEFM 2007: 247-256 |
13 | EE | Joel P. Self,
Eric G. Mercer:
On-the-Fly Dynamic Dead Variable Analysis.
SPIN 2007: 113-130 |
12 | EE | Neha Rungta,
Eric G. Mercer:
Generating Counter-Examples Through Randomized Guided Search.
SPIN 2007: 39-57 |
2006 |
11 | EE | Neha Rungta,
Eric G. Mercer:
An Improved Distance Heuristic Function for Directed Software Model Checking.
FMCAD 2006: 60-67 |
2005 |
10 | EE | Neha Rungta,
Eric G. Mercer:
A context-sensitive structural heuristic for guided search model checking.
ASE 2005: 410-413 |
9 | EE | Eric Mercer,
Michael Jones:
Model Checking Machine Code with the GNU Debugger.
SPIN 2005: 251-265 |
8 | EE | Rahul Kumar,
Eric G. Mercer:
Load Balancing Parallel Explicit State Model Checking.
Electr. Notes Theor. Comput. Sci. 128(3): 19-34 (2005) |
2004 |
7 | EE | Michael Jones,
Eric Mercer:
Explicit State Model Checking with Hopper.
SPIN 2004: 146-150 |
2003 |
6 | EE | Michael Jones,
Eric Mercer,
Tonglaga Bao,
Rahul Kumar,
Peter Lamborn:
Benchmarking Explicit State Parallel Model Checkers.
Electr. Notes Theor. Comput. Sci. 89(1): (2003) |
5 | EE | Hao Zheng,
Eric Mercer,
Chris J. Myers:
Modular verification of timed circuits using automatic abstraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003) |
2002 |
4 | EE | Tomoya Kitai,
Yusuke Oguro,
Tomohiro Yoneda,
Eric Mercer,
Chris J. Myers:
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method.
PRDC 2002: 210-220 |
3 | EE | Eric Mercer,
Chris J. Myers,
Tomohiro Yoneda:
Modular Synthesis of Timed Circuits using Partial Order Reduction.
Electr. Notes Theor. Comput. Sci. 65(6): (2002) |
2001 |
2 | EE | Kip C. Killpack,
Eric Mercer,
Chris J. Myers:
A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems.
ARVLSI 2001: 188-201 |
1 | EE | Hao Zheng,
Eric Mercer,
Chris J. Myers:
Automatic Abstraction for Verification of Timed Circuits and Systems.
CAV 2001: 182-193 |