Eric Mercer

Eric G. Mercer

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19EENeha Rungta, Eric G. Mercer: Guided model checking for programs with polymorphism. PEPM 2009: 21-30
18EENeha Rungta, Eric G. Mercer: A Meta Heuristic for Effectively Detecting Concurrency Errors. Haifa Verification Conference 2008: 23-37
17EEDaniel D. Walker, Eric G. Mercer, Kent E. Seamons: Or Best Offer: A Privacy Policy Negotiation Protocol. POLICY 2008: 173-180
16EERahul Kumar, Eric G. Mercer: Improving Live Sequence Chart to Automata Transformation for Verification. ECEASST 10: (2008)
15EENeha Rungta, Hyrum Carroll, Eric G. Mercer, Randall J. Roper, Mark J. Clement, Quinn Snell: Analyzing Gene Relationships for Down Syndrome with Labeled Transition Graphs. FMCAD 2007: 216-219
14EENeha Rungta, Eric G. Mercer: Hardness for Explicit State Software Model Checking Benchmarks. SEFM 2007: 247-256
13EEJoel P. Self, Eric G. Mercer: On-the-Fly Dynamic Dead Variable Analysis. SPIN 2007: 113-130
12EENeha Rungta, Eric G. Mercer: Generating Counter-Examples Through Randomized Guided Search. SPIN 2007: 39-57
11EENeha Rungta, Eric G. Mercer: An Improved Distance Heuristic Function for Directed Software Model Checking. FMCAD 2006: 60-67
10EENeha Rungta, Eric G. Mercer: A context-sensitive structural heuristic for guided search model checking. ASE 2005: 410-413
9EEEric Mercer, Michael Jones: Model Checking Machine Code with the GNU Debugger. SPIN 2005: 251-265
8EERahul Kumar, Eric G. Mercer: Load Balancing Parallel Explicit State Model Checking. Electr. Notes Theor. Comput. Sci. 128(3): 19-34 (2005)
7EEMichael Jones, Eric Mercer: Explicit State Model Checking with Hopper. SPIN 2004: 146-150
6EEMichael Jones, Eric Mercer, Tonglaga Bao, Rahul Kumar, Peter Lamborn: Benchmarking Explicit State Parallel Model Checkers. Electr. Notes Theor. Comput. Sci. 89(1): (2003)
5EEHao Zheng, Eric Mercer, Chris J. Myers: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003)
4EETomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220
3EEEric Mercer, Chris J. Myers, Tomohiro Yoneda: Modular Synthesis of Timed Circuits using Partial Order Reduction. Electr. Notes Theor. Comput. Sci. 65(6): (2002)
2EEKip C. Killpack, Eric Mercer, Chris J. Myers: A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. ARVLSI 2001: 188-201
1EEHao Zheng, Eric Mercer, Chris J. Myers: Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193

Coauthor Index

1Tonglaga Bao [6]
2Hyrum Carroll [15]
3Mark J. Clement [15]
4Michael Jones [6] [7] [9]
5Kip C. Killpack [2]
6Tomoya Kitai [4]
7Rahul Kumar [6] [8] [16]
8Peter Lamborn [6]
9Chris J. Myers [1] [2] [3] [4] [5]
10Yusuke Oguro [4]
11Randall J. Roper [15]
12Neha Rungta [10] [11] [12] [14] [15] [18] [19]
13Kent E. Seamons [17]
14Joel P. Self [13]
15Quinn Snell [15]
16Daniel D. Walker [17]
17Tomohiro Yoneda [3] [4]
18Hao Zheng [1] [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)