| 2005 |
|---|
| 6 | EE | Zhijun Huang,
Milos D. Ercegovac:
High-Performance Low-Power Left-to-Right Array Multiplier Design.
IEEE Trans. Computers 54(3): 272-283 (2005) |
| 2003 |
|---|
| 5 | EE | Zhijun Huang,
Milos D. Ercegovac:
High-Performance Left-to-Right Array Multiplier Design.
IEEE Symposium on Computer Arithmetic 2003: 4-11 |
| 4 | EE | Deming Chen,
Jason Cong,
Milos D. Ercegovac,
Zhijun Huang:
Performance-driven mapping for CPLD architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003) |
| 2002 |
|---|
| 3 | EE | Zhijun Huang,
Milos D. Ercegovac:
Two-dimensional signal gating for low-power array multiplier design.
ISCAS (1) 2002: 489-492 |
| 2001 |
|---|
| 2 | EE | Deming Chen,
Jason Cong,
Milos D. Ercegovac,
Zhijun Huang:
Performance-driven mapping for CPLD architectures.
FPGA 2001: 39-47 |
| 1999 |
|---|
| 1 | EE | Feng Zhou,
Zhijun Huang,
Jiarong Tong,
Pushan Tang:
An Analytical Delay Model for SRAM-Based FPGA Interconnections.
ASP-DAC 1999: 101-104 |
