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Zhijun Huang

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2005
6EEZhijun Huang, Milos D. Ercegovac: High-Performance Low-Power Left-to-Right Array Multiplier Design. IEEE Trans. Computers 54(3): 272-283 (2005)
2003
5EEZhijun Huang, Milos D. Ercegovac: High-Performance Left-to-Right Array Multiplier Design. IEEE Symposium on Computer Arithmetic 2003: 4-11
4EEDeming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003)
2002
3EEZhijun Huang, Milos D. Ercegovac: Two-dimensional signal gating for low-power array multiplier design. ISCAS (1) 2002: 489-492
2001
2EEDeming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47
1999
1EEFeng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang: An Analytical Delay Model for SRAM-Based FPGA Interconnections. ASP-DAC 1999: 101-104

Coauthor Index

1Deming Chen [2] [4]
2Jason Cong [2] [4]
3Milos D. Ercegovac [2] [3] [4] [5] [6]
4Pushan Tang [1]
5Jiarong Tong [1]
6Feng Zhou [1]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)