| 2008 |
|---|
| 9 | EE | Henry H. K. Tang,
Conal E. Murray,
Giovanni Fiorenza,
Kenneth P. Rodbell,
Michael S. Gordon,
David F. Heidel:
New simulation methodology for effects of radiation in semiconductor chip structures.
IBM Journal of Research and Development 52(3): 245-254 (2008) |
| 2007 |
|---|
| 8 | EE | Mary Yvonne Lanzerotti,
Giovanni Fiorenza,
Rick A. Rand:
Impact of interconnect length changes on effective materials properties (dielectric constant).
SLIP 2007: 73-80 |
| 2005 |
|---|
| 7 | EE | Gerald G. Lopez,
Giovanni Fiorenza,
Thomas J. Bucelot,
Phillip Restle,
Mary Yvonne Lanzerotti:
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.
ACM Great Lakes Symposium on VLSI 2005: 38-43 |
| 6 | EE | Mary Yvonne Lanzerotti,
Giovanni Fiorenza,
Rick A. Rand:
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry.
SLIP 2005: 43-50 |
| 5 | EE | Mary Yvonne Lanzerotti,
Giovanni Fiorenza,
Rick A. Rand:
Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements.
IBM Journal of Research and Development 49(4-5): 777-803 (2005) |
| 2004 |
|---|
| 4 | EE | Mary Yvonne Lanzerotti,
Giovanni Fiorenza,
Rick A. Rand:
Assessment of on-chip wire-length distribution models.
IEEE Trans. VLSI Syst. 12(10): 1108-1112 (2004) |
| 3 | EE | Mary Yvonne Lanzerotti,
Giovanni Fiorenza,
Rick A. Rand:
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models.
IEEE Trans. VLSI Syst. 12(12): 1330-1347 (2004) |
| 2003 |
|---|
| 2 | EE | Mary Y. L. Wisniewski,
Emmanuel Yashchin,
Robert L. Franch,
David P. Conrady,
Giovanni Fiorenza,
I. Cevdet Noyan:
Estimating the efficiency of collaborative problem-solving, with applications to chip design.
IBM Journal of Research and Development 47(1): 77-88 (2003) |
| 1 | EE | Mary Y. L. Wisniewski,
Emmanuel Yashchin,
Robert L. Franch,
David P. Conrady,
Daniel N. Maynard,
Giovanni Fiorenza,
I. Cevdet Noyan:
The physical design of on-chip interconnections.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 254-276 (2003) |
